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radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use

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Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Vincent Lejeune
2012-09-04 16:49:25 +02:00
parent 73dd82061e
commit 6a85725f13
2 changed files with 4 additions and 4 deletions
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src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+2 -2
View File
@@ -25,8 +25,8 @@
#define GET_INSTRINFO_ENUM
#include "AMDGPUGenInstrInfo.inc"
#define OPCODE_IS_ZERO_INT 0x00000045
#define OPCODE_IS_NOT_ZERO_INT 0x00000042
#define OPCODE_IS_ZERO_INT 0x00000042
#define OPCODE_IS_NOT_ZERO_INT 0x00000045
#define OPCODE_IS_ZERO 0x00000020
#define OPCODE_IS_NOT_ZERO 0x00000023
src/gallium/drivers/radeon/R600ISelLowering.cpp
+2 -2
View File
@@ -207,7 +207,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
.addReg(AMDGPU::PREDICATE_BIT)
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_ZERO)
.addImm(OPCODE_IS_NOT_ZERO)
.addImm(0); // Flags
TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
@@ -221,7 +221,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
.addReg(AMDGPU::PREDICATE_BIT)
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_ZERO_INT)
.addImm(OPCODE_IS_NOT_ZERO_INT)
.addImm(0); // Flags
TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))