i965/gen6/blorp: Set need_workaround_flush at top of blorp

Unconditionally set brw->need_workaround_flush at the top of gen6 blorp
state emission.

The art of emitting workaround flushes on Sandybridge is mysterious and
not fully understood. Ken and I believe that
intel_emit_post_sync_nonzero_flush() may be required when switching from
regular drawing to blorp.  This is an extra safety measure to prevent
undiscovered difficult-to-diagnose gpu hangs.

I verified that on ChromeOS, pre-patch, need_workaround_flush was not
set at the top of blorp, as Paul expected. To verify, I inserted the
following debug code at the top of gen6_blorp_exec(), restarted the ui,
and inspected the logs in /var/log/ui. The abort gets triggered so early
that the browser never appears on the display.

    static void
    gen6_blorp_exec(...)
    {
        if (!brw->need_workaround_flush) {
            fprintf(stderr, "chadv: %s:%d\n", __FILE__, __LINE__);
            abort();
        }
        ...
    }

CC: Kenneth Graunke <kenneth@whitecape.org>
CC: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

src/mesa/drivers/dri/i965/gen6_blorp.cpp

@@ -1023,7 +1023,6 @@ gen6_emit_hiz_workaround(struct brw_context *brw, enum gen6_hiz_op hiz_op)
     */
    if (hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE ||
        hiz_op == GEN6_HIZ_OP_HIZ_RESOLVE) {
-      brw->batch.need_workaround_flush = true;
       intel_emit_post_sync_nonzero_flush(brw);
       intel_emit_depth_stall_flushes(brw);
    }
@@ -1051,6 +1050,9 @@ gen6_blorp_exec(struct brw_context *brw,
 
    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 
+   /* Emit workaround flushes when we switch from drawing to blorping. */
+   brw->batch.need_workaround_flush = true;
+
    gen6_emit_hiz_workaround(brw, params->hiz_op);
    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
    gen6_emit_3dstate_sample_mask(brw,