AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radeon/llvm: Fix lowering of vbuild

Browse Source 
Some of the old AMDIL code was hard-coding subreg indices when creating
the VBUILD node, which was making it difficult to match the
vector_insert patterns.
This commit is contained in:
Tom Stellard
2012-09-11 15:24:32 -04:00
parent 70a50685a8
commit 6a5a4d59ce
7 changed files with 19 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
-2
View File
@@ -88,7 +88,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
// AMDIL DAG lowering
case ISD::SDIV: return LowerSDIV(Op, DAG);
case ISD::SREM: return LowerSREM(Op, DAG);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
// AMDGPU DAG lowering
@@ -336,7 +335,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const
NODE_NAME_CASE(CALL);
NODE_NAME_CASE(UMUL);
NODE_NAME_CASE(DIV_INF);
NODE_NAME_CASE(VBUILD);
NODE_NAME_CASE(RET_FLAG);
NODE_NAME_CASE(BRANCH_COND);
src/gallium/drivers/radeon/AMDGPUISelLowering.h
-2
View File
@@ -90,7 +90,6 @@ private:
SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
@@ -105,7 +104,6 @@ enum
// AMDIL ISD Opcodes
FIRST_NUMBER = ISD::BUILTIN_OP_END,
MAD, // 32bit Fused Multiply Add instruction
VBUILD, // scalar to vector mov instruction
CALL, // Function call based on a single integer
UMUL, // 32bit unsigned multiplication
DIV_INF, // Divide with infinity returned on zero divisor
src/gallium/drivers/radeon/AMDGPUInstructions.td
+7 -3
View File
@@ -154,9 +154,13 @@ class Insert_Element <ValueType elem_type, ValueType vec_type,
>;
// Vector Build pattern
class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
(IL_vbuild elemClass:$src),
(INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x)
class Vector_Build <ValueType vecType, RegisterClass vectorClass,
ValueType elemType, RegisterClass elemClass> : Pat <
(vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
(elemType elemClass:$z), (elemType elemClass:$w))),
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(vecType (IMPLICIT_DEF)), elemClass:$x, sel_x), elemClass:$y, sel_y),
elemClass:$z, sel_z), elemClass:$w, sel_w)
>;
// bitconvert pattern
src/gallium/drivers/radeon/AMDILISelLowering.cpp
-68
View File
@@ -162,7 +162,6 @@ void AMDGPUTargetLowering::InitAMDILLowering()
{
MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii];
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
setOperationAction(ISD::SDIVREM, VT, Expand);
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
@@ -217,7 +216,6 @@ void AMDGPUTargetLowering::InitAMDILLowering()
setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom);
// Use the default implementation.
setOperationAction(ISD::ConstantFP , MVT::f32 , Legal);
@@ -350,72 +348,6 @@ AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const
return DST;
}
SDValue
AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const
{
EVT VT = Op.getValueType();
SDValue Nodes1;
SDValue second;
SDValue third;
SDValue fourth;
DebugLoc DL = Op.getDebugLoc();
Nodes1 = DAG.getNode(AMDGPUISD::VBUILD,
DL,
VT, Op.getOperand(0));
#if 0
bool allEqual = true;
for (unsigned x = 1, y = Op.getNumOperands(); x < y; ++x) {
if (Op.getOperand(0) != Op.getOperand(x)) {
allEqual = false;
break;
}
}
if (allEqual) {
return Nodes1;
}
#endif
switch(Op.getNumOperands()) {
default:
case 1:
break;
case 4:
fourth = Op.getOperand(3);
if (fourth.getOpcode() != ISD::UNDEF) {
Nodes1 = DAG.getNode(
ISD::INSERT_VECTOR_ELT,
DL,
Op.getValueType(),
Nodes1,
fourth,
DAG.getConstant(7, MVT::i32));
}
case 3:
third = Op.getOperand(2);
if (third.getOpcode() != ISD::UNDEF) {
Nodes1 = DAG.getNode(
ISD::INSERT_VECTOR_ELT,
DL,
Op.getValueType(),
Nodes1,
third,
DAG.getConstant(6, MVT::i32));
}
case 2:
second = Op.getOperand(1);
if (second.getOpcode() != ISD::UNDEF) {
Nodes1 = DAG.getNode(
ISD::INSERT_VECTOR_ELT,
DL,
Op.getValueType(),
Nodes1,
second,
DAG.getConstant(5, MVT::i32));
}
break;
};
return Nodes1;
}
SDValue
AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
{
src/gallium/drivers/radeon/AMDILInstrInfo.td
-6
View File
@@ -124,12 +124,6 @@ def IL_mad : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>;
def IL_umul : SDNode<"AMDGPUISD::UMUL" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
//===----------------------------------------------------------------------===//
// Vector functions
//===----------------------------------------------------------------------===//
def IL_vbuild : SDNode<"AMDGPUISD::VBUILD", SDTIL_GenVecBuild,
[]>;
//===--------------------------------------------------------------------===//
// Custom Pattern DAG Nodes
//===--------------------------------------------------------------------===//
src/gallium/drivers/radeon/R600Instructions.td
+10 -10
View File
@@ -1239,23 +1239,23 @@ def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sel_x>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sel_y>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sel_z>;
def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sel_w>;
def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sel_x>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sel_y>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sel_z>;
def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sel_w>;
def : Vector_Build <v4f32, R600_Reg32>;
def : Vector_Build <v4i32, R600_Reg32>;
def : Vector_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
def : Vector_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
// bitconvert patterns
src/gallium/drivers/radeon/SIInstructions.td
+2 -2
View File
@@ -1058,8 +1058,8 @@ def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 5, sel_y>;
def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 6, sel_z>;
def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 7, sel_w>;
def : Vector_Build <v4f32, VReg_32>;
def : Vector_Build <v4i32, SReg_32>;
def : Vector_Build <v4f32, VReg_128, f32, VReg_32>;
def : Vector_Build <v4i32, SReg_128, i32, SReg_32>;
def : BitConvert <i32, f32, SReg_32>;
def : BitConvert <i32, f32, VReg_32>;