i965/vec4: Replace vec4_instruction::regs_written with ::size_written field in bytes.

The previous regs_written field can be recovered by rewriting each
rvalue reference of regs_written like 'x = i.regs_written' to 'x =
DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference
like 'i.regs_written = x' to 'i.size_written = x * reg_unit'.

For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible.  I'll come
back later to clean up any ugliness introduced here.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

src/mesa/drivers/dri/i965/brw_ir_vec4.h

@@ -264,7 +264,8 @@ inline unsigned
 regs_written(const vec4_instruction *inst)
 {
    /* XXX - Take into account register-misaligned offsets correctly. */
-   return inst->regs_written;
+   assert(inst->dst.file != UNIFORM && inst->dst.file != IMM);
+   return DIV_ROUND_UP(inst->size_written, REG_SIZE);
 }
 
 /**

src/mesa/drivers/dri/i965/brw_vec4.cpp

@@ -1133,7 +1133,7 @@ vec4_visitor::opt_register_coalesce()
                                                   inst) {
          _scan_inst = scan_inst;
 
-         if (inst->src[0].in_range(scan_inst->dst, scan_inst->regs_written)) {
+         if (inst->src[0].in_range(scan_inst->dst, DIV_ROUND_UP(scan_inst->size_written, REG_SIZE))) {
             /* Found something writing to the reg we want to coalesce away. */
             if (to_mrf) {
                /* SEND instructions can't have MRF as a destination. */
@@ -1169,7 +1169,7 @@ vec4_visitor::opt_register_coalesce()
             }
 
             /* This doesn't handle coalescing of multiple registers. */
-            if (scan_inst->regs_written > 1)
+            if (scan_inst->size_written > REG_SIZE)
                break;
 
 	    /* Mark which channels we found unconditional writes for. */
@@ -1197,7 +1197,7 @@ vec4_visitor::opt_register_coalesce()
          /* If somebody else writes the same channels of our destination here,
           * we can't coalesce before that.
           */
-         if (inst->dst.in_range(scan_inst->dst, scan_inst->regs_written) &&
+         if (inst->dst.in_range(scan_inst->dst, DIV_ROUND_UP(scan_inst->size_written, REG_SIZE)) &&
              (inst->dst.writemask & scan_inst->dst.writemask) != 0) {
             break;
          }

src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp

@@ -69,7 +69,7 @@ opt_cmod_propagation_local(bblock_t *block)
       bool read_flag = false;
       foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) {
          if (inst->src[0].in_range(scan_inst->dst,
-                                   scan_inst->regs_written)) {
+                                   DIV_ROUND_UP(scan_inst->size_written, REG_SIZE))) {
             if ((scan_inst->predicate && scan_inst->opcode != BRW_OPCODE_SEL) ||
                 scan_inst->dst.offset / REG_SIZE != inst->src[0].offset / REG_SIZE ||
                 (scan_inst->dst.writemask != WRITEMASK_X &&

src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

@@ -72,7 +72,7 @@ is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
    if (!src || src->file != VGRF)
       return false;
 
-   return (src->in_range(inst->dst, inst->regs_written) &&
+   return (src->in_range(inst->dst, DIV_ROUND_UP(inst->size_written, REG_SIZE)) &&
            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
 }
 

src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

@@ -129,7 +129,7 @@ instructions_match(vec4_instruction *a, vec4_instruction *b)
           a->shadow_compare == b->shadow_compare &&
           a->dst.writemask == b->dst.writemask &&
           a->force_writemask_all == b->force_writemask_all &&
-          a->regs_written == b->regs_written &&
+          a->size_written == b->size_written &&
           operands_match(a, b);
 }
 

src/mesa/drivers/dri/i965/brw_vec4_nir.cpp

@@ -839,7 +839,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
          vec4_builder(this).at_end().annotate(current_annotation, base_ir);
       const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
       bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
-         ->regs_written = 2;
+         ->size_written = 2 * REG_SIZE;
       break;
    }
 

src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp

@@ -145,7 +145,7 @@ namespace brw {
             vec4_instruction *inst =
                bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg));
             inst->mlen = sz;
-            inst->regs_written = ret_sz;
+            inst->size_written = ret_sz * REG_SIZE;
             inst->header_size = header_sz;
             inst->predicate = pred;
 

src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

@@ -46,7 +46,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
    this->predicate = BRW_PREDICATE_NONE;
    this->predicate_inverse = false;
    this->target = 0;
-   this->regs_written = (dst.file == BAD_FILE ? 0 : 1);
+   this->size_written = (dst.file == BAD_FILE ? 0 : REG_SIZE);
    this->shadow_compare = false;
    this->ir = NULL;
    this->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;

src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp

@@ -370,7 +370,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
    src_reg zero(brw_imm_f(0.0f));
    bld.ADD(offset(dest, 2), src0, src1);
    bld.emit(SHADER_OPCODE_TEX, dest, src2)
-      ->regs_written = 4;
+      ->size_written = 4 * REG_SIZE;
    bld.CMP(bld.null_reg_f(), offset(src_reg(dest), 2), zero, BRW_CONDITIONAL_GE);
 
    /* = Before =