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intel/brw: Add missing bits in 3-src SWSB encoding for Xe2+

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Fix invalid SWSB annotation in dEQP-VK.glsl.builtin.precision.mix.mediump.vec4 for LNL.

Fixes: 4a24f49b57 ("intel/compiler/xe2: Implement codegen of three-source instructions.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32846>
This commit is contained in:
Caio Oliveira
2025-01-02 10:39:49 -08:00
committed by Marge Bot
parent 51b0bad30b
commit 6968794c50
1 changed files with 1 additions and 1 deletions
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src/intel/compiler/brw_eu_inst.h
+1 -1
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@@ -431,7 +431,7 @@ F(3src_no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1)
F(3src_no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1)
F(3src_mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31)
FK(3src_access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
F(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8)
F20(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
/* Bit 7 is Reserved (for future Opcode expansion) */
F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
/** @} */