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radeonsi/video: Remove support for interlaced buffers

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This is not used anymore with VDPAU removed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36632>
This commit is contained in:
David Rosca
2025-08-07 14:27:25 +02:00
committed by Marge Bot
parent 223d3ec433
commit 6954460899
4 changed files with 6 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/radeon_uvd.c
+4 -15
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@@ -1441,14 +1441,8 @@ void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
if (chroma)
msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
if (msg->body.decode.dt_field_mode) {
msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
if (chroma)
msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
} else {
msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
}
msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
if (chroma) {
assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
@@ -1466,13 +1460,8 @@ void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
msg->body.decode.dt_wa_chroma_bottom_offset = luma->u.gfx9.swizzle_mode;
msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
if (msg->body.decode.dt_field_mode) {
msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
} else {
msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
}
msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
msg->body.decode.dt_surf_tile_config = 0;
break;
}
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
+2 -10
View File
@@ -1769,21 +1769,13 @@ static struct pb_buffer_lean *rvcn_dec_message_decode(struct radeon_decoder *dec
decode->dt_tiling_mode = 0;
decode->dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode;
decode->dt_array_mode = dec->addr_gfx_mode;
decode->dt_field_mode = ((struct vl_video_buffer *)out_surf)->base.interlaced;
decode->dt_surf_tile_config = 0;
decode->dt_uv_surf_tile_config = 0;
decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset | (luma->surface.tile_swizzle << 8);
decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset| (chroma->surface.tile_swizzle << 8);
if (decode->dt_field_mode) {
decode->dt_luma_bottom_offset =
decode->dt_luma_top_offset + luma->surface.u.gfx9.surf_slice_size;
decode->dt_chroma_bottom_offset =
decode->dt_chroma_top_offset + chroma->surface.u.gfx9.surf_slice_size;
} else {
decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
}
decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
decode->mif_wrc_en = sscreen->info.vcn_ip_version >= VCN_3_0_0;
if (dec->stream_type == RDECODE_CODEC_AV1)
decode->db_pitch_uv = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w;
src/gallium/drivers/radeonsi/si_get.c
-19
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@@ -127,17 +127,12 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return PIPE_VIDEO_VPP_BLEND_MODE_NONE;
case PIPE_VIDEO_CAP_PREFERRED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
return false;
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_REQUIRES_FLUSH_ON_END_FRAME:
/* true: VPP flush function will be called within vaEndPicture() */
/* false: VPP flush function will be skipped */
return false;
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
/* for VPE we prefer non-interlaced buffer */
return false;
case PIPE_VIDEO_CAP_VPP_SUPPORT_HDR_INPUT:
if (debug_get_bool_option("AMDGPU_SIVPE_SUPPORT_HDR_INPUT", false))
return true;
@@ -200,10 +195,6 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return PIPE_FORMAT_P010;
else
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
return false;
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
return false;
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_STACKED_FRAMES:
@@ -509,16 +500,6 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
else
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
return false;
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
enum pipe_video_format format = u_reduce_video_profile(profile);
if (format >= PIPE_VIDEO_FORMAT_HEVC)
return false;
return true;
}
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_MAX_LEVEL:
src/gallium/drivers/radeonsi/si_uvd.c
-2
View File
@@ -111,8 +111,6 @@ static struct pb_buffer_lean *si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_vid
enum ruvd_surface_type type =
(sscreen->info.gfx_level >= GFX9) ? RUVD_SURFACE_TYPE_GFX9 : RUVD_SURFACE_TYPE_LEGACY;
msg->body.decode.dt_field_mode = buf->base.interlaced;
si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
return luma->buffer.buf;