AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radeonsi: move get_cache_policy into si_cp_dma.c

Browse Source 
it's the only user

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
This commit is contained in:
Marek Olšák
2024-08-19 20:44:56 -04:00
parent 8c872d46a8
commit 68adac4d28
7 changed files with 24 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/si_compute_blit.c
+2 -16
View File
@@ -12,18 +12,6 @@
#include "util/u_pack_color.h"
#include "ac_nir_meta.h"
/* Determine the cache policy. */
static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_coherency coher)
{
if ((sctx->gfx_level >= GFX9 && (coher == SI_COHERENCY_CB_META ||
coher == SI_COHERENCY_DB_META ||
coher == SI_COHERENCY_CP)) ||
(sctx->gfx_level >= GFX7 && coher == SI_COHERENCY_SHADER))
return L2_LRU; /* it's faster if L2 doesn't evict anything */
return L2_BYPASS;
}
unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
enum si_cache_policy cache_policy)
{
@@ -369,7 +357,7 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
assert(clear_value_size == 4);
assert(!(flags & SI_OP_CS_RENDER_COND_ENABLE));
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, offset, aligned_size, *clear_value,
flags, coher, get_cache_policy(sctx, coher));
flags, coher);
}
offset += aligned_size;
@@ -408,7 +396,6 @@ void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct p
return;
enum si_coherency coher = SI_COHERENCY_SHADER;
enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
si_improve_sync_flags(sctx, dst, src, &flags);
@@ -416,8 +403,7 @@ void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct p
coher, 0, true))
return;
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size, flags, coher,
cache_policy);
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size, flags, coher);
}
void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
src/gallium/drivers/radeonsi/si_cp_dma.c
+15 -4
View File
@@ -21,6 +21,17 @@
#define CP_DMA_PFP_SYNC_ME (1 << 4)
#define CP_DMA_SRC_IS_GDS (1 << 5)
static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_coherency coher)
{
if ((sctx->gfx_level >= GFX9 && (coher == SI_COHERENCY_CB_META ||
coher == SI_COHERENCY_DB_META ||
coher == SI_COHERENCY_CP)) ||
(sctx->gfx_level >= GFX7 && coher == SI_COHERENCY_SHADER))
return L2_LRU;
return L2_BYPASS;
}
/* The max number of bytes that can be copied per packet. */
static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
{
@@ -178,12 +189,12 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
struct pipe_resource *dst, uint64_t offset, uint64_t size,
unsigned value, unsigned user_flags, enum si_coherency coher,
enum si_cache_policy cache_policy)
unsigned value, unsigned user_flags, enum si_coherency coher)
{
struct si_resource *sdst = si_resource(dst);
uint64_t va = (sdst ? sdst->gpu_address : 0) + offset;
bool is_first = true;
enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
assert(!sctx->screen->info.cp_sdma_ge_use_system_memory_scope);
assert(size && size % 4 == 0);
@@ -289,14 +300,14 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, uns
*/
void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
unsigned size, unsigned user_flags, enum si_coherency coher,
enum si_cache_policy cache_policy)
unsigned size, unsigned user_flags, enum si_coherency coher)
{
uint64_t main_dst_offset, main_src_offset;
unsigned skipped_size = 0;
unsigned realign_size = 0;
unsigned gds_flags = (dst ? 0 : CP_DMA_DST_IS_GDS) | (src ? 0 : CP_DMA_SRC_IS_GDS);
bool is_first = true;
enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
assert(!sctx->screen->info.cp_sdma_ge_use_system_memory_scope);
assert(size);
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
+1 -1
View File
@@ -59,7 +59,7 @@ void si_init_cp_reg_shadowing(struct si_context *sctx)
/* We need to clear the shadowed reg buffer. */
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowing.registers->b.b,
0, sctx->shadowing.registers->bo_size, 0, SI_OP_SYNC_AFTER,
SI_COHERENCY_CP, L2_BYPASS);
SI_COHERENCY_CP);
/* Create the shadowing preamble. (allocate enough dwords because the preamble is large) */
struct si_pm4_state *shadowing_preamble = si_pm4_create_sized(sctx->screen, 256, false);
src/gallium/drivers/radeonsi/si_pipe.c
+1 -1
View File
@@ -1089,7 +1089,7 @@ static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
if (test_flags & DBG(TEST_VMFAULT_CP)) {
si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, SI_OP_SYNC_BEFORE_AFTER,
SI_COHERENCY_NONE, L2_BYPASS);
SI_COHERENCY_NONE);
ctx->flush(ctx, NULL, 0);
puts("VM fault test: CP - done.");
}
src/gallium/drivers/radeonsi/si_pipe.h
+2 -4
View File
@@ -1544,12 +1544,10 @@ void si_init_compute_blit_functions(struct si_context *sctx);
void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
struct pipe_resource *dst, uint64_t offset, uint64_t size,
unsigned value, unsigned user_flags, enum si_coherency coher,
enum si_cache_policy cache_policy);
unsigned value, unsigned user_flags, enum si_coherency coher);
void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
unsigned size, unsigned user_flags, enum si_coherency coher,
enum si_cache_policy cache_policy);
unsigned size, unsigned user_flags, enum si_coherency coher);
void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
unsigned size, unsigned dst_sel, unsigned engine, const void *data);
void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
src/gallium/drivers/radeonsi/si_shader.c
+1 -2
View File
@@ -982,8 +982,7 @@ static void post_upload_binary(struct si_screen *sscreen, struct si_shader *shad
* them available.
*/
si_cp_dma_copy_buffer(upload_ctx, &shader->bo->b.b, staging, 0, staging_offset,
binary_size, SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER,
sscreen->info.gfx_level >= GFX7 ? L2_LRU : L2_BYPASS);
binary_size, SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER);
upload_ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_L2;
#if 0 /* debug: validate whether the copy was successful */
src/gallium/drivers/radeonsi/si_test_dma_perf.c
+2 -4
View File
@@ -228,8 +228,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
continue;
}
si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size,
SI_OP_SYNC_BEFORE_AFTER, SI_COHERENCY_SHADER,
sctx->gfx_level >= GFX7 ? L2_LRU : L2_BYPASS);
SI_OP_SYNC_BEFORE_AFTER, SI_COHERENCY_SHADER);
} else {
/* CP DMA clears must be aligned to 4 bytes. */
if (dst_offset % 4 || size % 4 ||
@@ -241,8 +240,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
assert(clear_value_size == 4);
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, dst_offset, size,
clear_value[0], SI_OP_SYNC_BEFORE_AFTER,
SI_COHERENCY_SHADER,
sctx->gfx_level >= GFX7 ? L2_LRU : L2_BYPASS);
SI_COHERENCY_SHADER);
}
} else {
/* Compute */