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freedreno: Fix CP_COND_REG_EXEC bit positions

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Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
This commit is contained in:
Connor Abbott
2020-01-28 13:19:25 +01:00
committed by Marge Bot
parent 8be81f8a2a
commit 65197a3ac1
1 changed files with 3 additions and 3 deletions
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src/freedreno/registers/adreno_pm4.xml
+3 -3
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@@ -1473,11 +1473,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
-->
<!-- RM6_BINNING -->
<bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
<bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
<!-- all others -->
<bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
<bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
<!-- RM6_BYPASS -->
<bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
<bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
<bitfield name="MODE" low="28" high="31" type="compare_mode"/>
</reg32>