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iris: Move Wa_1806527549 and enable by default

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Move Wa_1806527549 into `iris_init_render_context` and
set HIZ_CHICKEN (7018h) bit = 1 by default for TGL.

Cc: mesa-stable
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17778>
This commit is contained in:
Mykhailo Skorokhodov
2022-07-30 03:32:38 +03:00
parent 188d1e2b20
commit 6498328210
1 changed files with 11 additions and 9 deletions
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src/gallium/drivers/iris/iris_state.c
+11 -9
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@@ -1102,6 +1102,17 @@ iris_init_render_context(struct iris_batch *batch)
}
#endif
#if GFX_VERx10 == 120
/* Wa_1806527549 says to disable the following HiZ optimization when the
* depth buffer is D16_UNORM. We've found the WA to help with more depth
* buffer configurations however, so we always disable it just to be safe.
*/
iris_emit_reg(batch, GENX(HIZ_CHICKEN), reg) {
reg.HZDepthTestLEGEOptimizationDisable = true;
reg.HZDepthTestLEGEOptimizationDisableMask = true;
}
#endif
upload_pixel_hashing_tables(batch);
/* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
@@ -5745,15 +5756,6 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
reg.HIZPlaneOptimizationdisablebitMask = true;
}
/* Wa_1806527549
*
* Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM.
*/
iris_emit_reg(batch, GENX(HIZ_CHICKEN), reg) {
reg.HZDepthTestLEGEOptimizationDisable = fmt_is_d16;
reg.HZDepthTestLEGEOptimizationDisableMask = true;
}
ice->state.genx->depth_reg_mode =
fmt_is_d16 ? IRIS_DEPTH_REG_MODE_D16 : IRIS_DEPTH_REG_MODE_HW_DEFAULT;
#endif