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freedreno/ir3: make reg array dynamic

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To use fanin's to group registers in an array, we can potentially have a
much larger array of registers.  Rather than continuing to bump up the
array size, just make it dynamically allocated when the instruction is
created.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
2015-01-07 11:52:32 -05:00
parent 9a9f2a893b
commit 63e5b72da8
4 changed files with 50 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/freedreno/ir3/ir3.c
+39 -7
View File
@@ -648,11 +648,27 @@ struct ir3_block * ir3_block_create(struct ir3 *shader,
return block;
}
struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
int category, opc_t opc)
static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
{
struct ir3_instruction *instr =
ir3_alloc(block->shader, sizeof(struct ir3_instruction));
struct ir3_instruction *instr;
unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
char *ptr = ir3_alloc(block->shader, sz);
instr = (struct ir3_instruction *)ptr;
ptr += sizeof(*instr);
instr->regs = (struct ir3_register **)ptr;
#ifdef DEBUG
instr->regs_max = nreg;
#endif
return instr;
}
struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
int category, opc_t opc, int nreg)
{
struct ir3_instruction *instr = instr_create(block, nreg);
instr->block = block;
instr->category = category;
instr->opc = opc;
@@ -660,13 +676,27 @@ struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
return instr;
}
struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
int category, opc_t opc)
{
/* NOTE: we could be slightly more clever, at least for non-meta,
* and choose # of regs based on category.
*/
return ir3_instr_create2(block, category, opc, 4);
}
/* only used by old compiler: */
struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
{
struct ir3_instruction *new_instr =
ir3_alloc(instr->block->shader, sizeof(struct ir3_instruction));
struct ir3_instruction *new_instr = instr_create(instr->block,
instr->regs_count);
struct ir3_register **regs;
unsigned i;
regs = new_instr->regs;
*new_instr = *instr;
new_instr->regs = regs;
insert_instr(instr->block->shader, new_instr);
/* clone registers: */
@@ -685,7 +715,9 @@ struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
int num, int flags)
{
struct ir3_register *reg = reg_create(instr->block->shader, num, flags);
assert(instr->regs_count < ARRAY_SIZE(instr->regs));
#ifdef DEBUG
debug_assert(instr->regs_count < instr->regs_max);
#endif
instr->regs[instr->regs_count++] = reg;
return reg;
}
src/gallium/drivers/freedreno/ir3/ir3.h
+6 -3
View File
@@ -106,8 +106,6 @@ struct ir3_register {
};
};
#define IR3_INSTR_SRCS 10
struct ir3_instruction {
struct ir3_block *block;
int category;
@@ -166,8 +164,11 @@ struct ir3_instruction {
IR3_INSTR_MARK = 0x1000,
} flags;
int repeat;
#ifdef DEBUG
unsigned regs_max;
#endif
unsigned regs_count;
struct ir3_register *regs[1 + IR3_INSTR_SRCS];
struct ir3_register **regs;
union {
struct {
char inv;
@@ -320,6 +321,8 @@ struct ir3_block * ir3_block_create(struct ir3 *shader,
struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
int category, opc_t opc);
struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
int category, opc_t opc, int nreg);
struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
const char *ir3_instr_name(struct ir3_instruction *instr);
src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+2 -2
View File
@@ -1365,7 +1365,7 @@ trans_samp(const struct instr_translater *t,
reg = ir3_reg_create(instr, 0, IR3_REG_SSA);
collect = ir3_instr_create(ctx->block, -1, OPC_META_FI);
collect = ir3_instr_create2(ctx->block, -1, OPC_META_FI, 12);
ir3_reg_create(collect, 0, 0);
for (i = 0; i < 4; i++) {
if (tinf.src_wrmask & (1 << i))
@@ -1403,7 +1403,7 @@ trans_samp(const struct instr_translater *t,
reg = ir3_reg_create(instr, 0, IR3_REG_SSA);
collect = ir3_instr_create(ctx->block, -1, OPC_META_FI);
collect = ir3_instr_create2(ctx->block, -1, OPC_META_FI, 5);
ir3_reg_create(collect, 0, 0);
if (inst->Texture.NumOffsets) {
src/gallium/drivers/freedreno/ir3/ir3_sched.c
+3 -1
View File
@@ -211,7 +211,7 @@ static unsigned delay_calc(struct ir3_sched_ctx *ctx,
static int trysched(struct ir3_sched_ctx *ctx,
struct ir3_instruction *instr)
{
struct ir3_instruction *srcs[ARRAY_SIZE(instr->regs) - 1];
struct ir3_instruction *srcs[64];
struct ir3_instruction *src;
unsigned i, delay, nsrcs = 0;
@@ -219,6 +219,8 @@ static int trysched(struct ir3_sched_ctx *ctx,
if (instr->flags & IR3_INSTR_MARK)
return 0;
debug_assert(instr->regs_count < ARRAY_SIZE(srcs));
/* figure out our src's: */
for (i = 1; i < instr->regs_count; i++) {
struct ir3_register *reg = instr->regs[i];