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radv: only load 3x32-bit elements when emitting draws with mesh shader

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27488>
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Samuel Pitoiset
2024-02-06 16:14:30 +01:00
committed by Marge Bot
parent 0296196d32
commit 63b238e84e
1 changed files with 1 additions and 1 deletions
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src/amd/vulkan/radv_device_generated_commands.c
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@@ -1168,7 +1168,7 @@ dgc_emit_draw_mesh_tasks(nir_builder *b, struct dgc_cmdbuf *cs, nir_def *stream_
nir_def *vtx_base_sgpr = load_param16(b, vtx_base_sgpr);
nir_def *stream_offset = nir_iadd(b, draw_params_offset, stream_base);
nir_def *draw_data = nir_load_ssbo(b, 4, 32, stream_buf, stream_offset);
nir_def *draw_data = nir_load_ssbo(b, 3, 32, stream_buf, stream_offset);
nir_def *x = nir_channel(b, draw_data, 0);
nir_def *y = nir_channel(b, draw_data, 1);
nir_def *z = nir_channel(b, draw_data, 2);