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ir3: Assemble and disassemble .clp modifier

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32671>
This commit is contained in:
Connor Abbott
2024-12-03 17:38:10 -05:00
committed by Marge Bot
parent 655934eef7
commit 63959bb716
7 changed files with 23 additions and 6 deletions
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src/freedreno/ir3/ir3.h
+3
View File
@@ -413,6 +413,9 @@ typedef enum ir3_instruction_flags {
* non-resident page. Only allowed for cat5 texture loads and ldib.
*/
IR3_INSTR_RCK = BIT(24),
/* Clamp computed LOD using the given minimum. Only for cat5. */
IR3_INSTR_CLP = BIT(25),
} ir3_instruction_flags;
struct ir3_instruction {
src/freedreno/ir3/ir3_lexer.l
+1
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@@ -494,6 +494,7 @@ static int parse_reg(const char *str)
"u" return 'u';
"v" return 'v';
"rck" return T_RCK;
"clp" return T_CLP;
"base"[0-9]+ ir3_yylval.num = strtol(yytext+4, NULL, 10); return T_BASE;
"offset"[0-9]+ ir3_yylval.num = strtol(yytext+6, NULL, 10); return T_OFFSET;
"uniform" return T_UNIFORM;
src/freedreno/ir3/ir3_parser.y
+2
View File
@@ -770,6 +770,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
%token <tok> T_NONUNIFORM
%token <tok> T_IMM
%token <tok> T_RCK
%token <tok> T_CLP
%token <tok> T_NAN
%token <tok> T_INF
@@ -1231,6 +1232,7 @@ cat5_flag: '.' T_3D { instr->flags |= IR3_INSTR_3D; }
| '.' T_BASE { instr->flags |= IR3_INSTR_B; instr->cat5.tex_base = $2; }
| '.' T_W { instr->cat5.cluster_size = $2; }
| '.' T_RCK { instr->flags |= IR3_INSTR_RCK; }
| '.' T_CLP { instr->flags |= IR3_INSTR_CLP; }
cat5_flags:
| cat5_flag cat5_flags
src/freedreno/ir3/tests/disasm.c
+6
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@@ -457,6 +457,9 @@ static const struct test {
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d */
INSTR_6XX(a0c01f04_0cc00005, "sam (f32)(xyzw)r1.x, r0.z, s#6, t#6"),
/* custom */
INSTR_6XX(a0c01f04_0cc40005, "sam.clp (f32)(xyzw)r1.x, r0.z, r0.x, s#6, t#6"),
/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.fragment.sampler2d */
INSTR_4XX(a0c81f02_00800001, "sam.s2en.uniform (f32)(xyzw)r0.z, r0.x, hr1.x"), /* sam.s2en.mode0 (f32)(xyzw)r0.z, r0.x, hr1.x */ /* same for 5xx */
INSTR_6XX(a0c81f07_0100000b, "sam.s2en.uniform (f32)(xyzw)r1.w, r1.y, hr2.x"), /* sam.s2en.mode0 (f32)(xyzw)r1.w, r1.y, hr2.x */
@@ -465,6 +468,9 @@ static const struct test {
INSTR_4XX(a0c81f02_80800001, "sam.s2en.nonuniform (f32)(xyzw)r0.z, r0.x, hr1.x"), /* sam.s2en.uniform (f32)(xyzw)r0.z, r0.x, hr1.x */ /* same for 5xx */
INSTR_6XX(a0c81f07_8100000b, "sam.s2en.nonuniform (f32)(xyzw)r1.w, r1.y, hr2.x"), /* sam.s2en.mode4 (f32)(xyzw)r1.w, r1.y, hr2.x */
/* custom */
INSTR_6XX(a1083f06_c0240805, "samb.base0.clp (u32)(xyzw)r1.z, r0.z, r1.x, s#1, t#0"), /* sam.s2en.mode4.clp (f32)(xyzw)r1.w, r1.y, hr2.x */
/* NonUniform: */
/* dEQP-VK.descriptor_indexing.storage_buffer */
INSTR_6XX(c0260c0a_0a61b180, "ldib.b.untyped.1d.u32.4.nonuniform.base0 r2.z, r2.z, r1.z"),
src/freedreno/isa/ir3-cat5.xml
+9 -4
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@@ -56,7 +56,7 @@ SOFTWARE.
The "normal" case, ie. not s2en (indirect) and/or bindless
</doc>
<display>
{SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{1D}{RCK} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SAMP}{TEX}
{SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{1D}{CLP}{RCK} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SAMP}{TEX}
</display>
<derived name="DST_HALF" expr="#type-half" type="bool" display="h"/>
<field name="FULL" pos="0" type="bool"/>
@@ -69,6 +69,7 @@ SOFTWARE.
<param name="NUM_SRC"/>
<param name="HALF"/>
<param name="O"/>
<param name="CLP"/>
<param name="SRC2_IMM_OFFSET"/>
</field>
<!--
@@ -136,7 +137,7 @@ SOFTWARE.
The s2en (indirect) or bindless case
</doc>
<display>
{SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{S2EN}{UNIFORM}{NONUNIFORM}{BASE}{1D}{RCK} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SRC3}{A1}
{SY}{JP}{NAME}{3D}{A}{O}{P}{SV}{S2EN}{UNIFORM}{NONUNIFORM}{BASE}{1D}{CLP}{RCK} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SRC3}{A1}
</display>
<field name="BASE_HI" low="19" high="20" type="uint"/>
<field name="SRC3" low="21" high="28" type="#cat5-src3">
@@ -161,13 +162,15 @@ SOFTWARE.
</bitset>
<bitset name="#instruction-cat5-tex" extends="#instruction-cat5-tex-base">
<pattern pos="18">0</pattern>
<field name="CLP" pos="18" type="bool" display=".clp"/>
<field name="SV" pos="50" type="bool" display=".s"/>
<field name="P" pos="53" type="bool" display=".p"/>
<derived name="1D" expr="#false" type="bool" display=""/>
<encode>
<map name="SV">!!(src->flags &amp; IR3_INSTR_S)</map>
<map name="P">!!(src->flags &amp; IR3_INSTR_P)</map>
<map name="CLP">!!(src->flags &amp; IR3_INSTR_CLP)</map>
</encode>
</bitset>
@@ -177,6 +180,7 @@ SOFTWARE.
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
<derived name="CLP" expr="#false" type="bool" display=""/>
<!-- Not sure what this field does exactly but isam.v does not work
without it set. The blob disassembles it as .1d when not set. -->
@@ -510,6 +514,7 @@ SOFTWARE.
<bitset name="#instruction-cat5-brcst" extends="#instruction-cat5">
<pattern pos="18">0</pattern>
<pattern pos="50">0</pattern>
<derived name="CLP" expr="#false" type="bool" display=""/>
</bitset>
<bitset name="brcst.active" extends="#instruction-cat5-brcst">
@@ -635,7 +640,7 @@ SOFTWARE.
<bitset name="#cat5-src2" size="8">
<override>
<expr>{O} || ({NUM_SRC} > 1)</expr>
<expr>{O} || {CLP} || ({NUM_SRC} > 1)</expr>
<display>
, {HALF}{SRC}
</display>
src/freedreno/tests/reference/crash.log
+1 -1
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@@ -3400,7 +3400,7 @@ shader-blocks:
:7:0001:0001[edc6145bx_11fa09c3x] no match: edc6145b11fa09c3
:2:0002:0002[41440087x_008c504ax] ceil.f hr33.w, (neg)hc18.z ; dontcare bits in ceil.f: 00040000008c0000
:0:0003:0003[14183488x_d5c04509x] no match: 14183488d5c04509
:5:0004:0004[a52373bdx_8ff7c071x] no match: a52373bd8ff7c071
:5:0004:0004[a52373bdx_8ff7c071x] samgp0.3d.a.p.clp.rck (xy)r47.y, r14.x, r56.x, s#15, t#71 ; dontcare bits in samgp0: 0000000000020000, WARNING: unexpected bits[19:20] in #instruction-cat5-tex-base: 0000000000000002 vs 0000000000000000
:1:0005:0005[39301c43x_1d826d16x] no match: 39301c431d826d16
-----------------------------------------------
8192 (0x2000) bytes
src/freedreno/tests/reference/prefetch-test.log
+1 -1
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@@ -140888,7 +140888,7 @@ shader-blocks:
:0:0051:0063[19d70515x_81d857bex] no match: 19d7051581d857be
:3:0052:0064[7972f999x_e4df0ecbx] (sy)(ss)(jp)(rpt1)(ul)mad.s16 r38.y, (r)hc<a0.x + -309>, (neg)hr57.y, (neg)(r)(last)hr55.w
:6:0053:0066[dda7eb4fx_f96f6ddfx] no match: dda7eb4ff96f6ddf
:5:0054:0067[a4e7fe75x_ab4ffb7fx] no match: a4e7fe75ab4ffb7f
:5:0054:0067[a4e7fe75x_ab4ffb7fx] gather4a.3d.a.p.s.clp.rck (yzw)r29.y, r47.w, r63.y, s#10, t#85 ; dontcare bits in gather4a: 0000000000020000, WARNING: unexpected bits[19:20] in #instruction-cat5-tex-base: 0000000000000001 vs 0000000000000000, WARNING: unexpected bits[47:47] in #instruction-cat5: 0000000000000001 vs 0000000000000000
:6:0055:0068[d1937f77x_effcfeefx] no match: d1937f77effcfeef
:0:0056:0069[1134c8d0x_34200204x] (sy)jump #874512900 ; dontcare bits in jump: 0034c8d000000000
:5:0057:0070[ac44c0eax_60215b2ex] (jp)gather4g.s (s16)()hr58.z, hr37.w, s#1, t#48 ; WARNING: unexpected bits[47:47] in #instruction-cat5: 0000000000000001 vs 0000000000000000, WARNING: unexpected bits[0:7] in #cat5-src2: 00000000000000ad vs 0000000000000000