swr/rast: Miscellaneous viewport array code changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
This commit is contained in:
@@ -450,16 +450,22 @@ void SIMDCALL BinTrianglesImpl(
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typename SIMD_T::Float vRecipW1 = SIMD_T::set1_ps(1.0f);
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typename SIMD_T::Float vRecipW2 = SIMD_T::set1_ps(1.0f);
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typename SIMD_T::Integer viewportIdx = SIMD_T::set1_epi32(0);
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typename SIMD_T::Integer viewportIdx = SIMD_T::setzero_si();
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typename SIMD_T::Vec4 vpiAttrib[3];
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typename SIMD_T::Integer vpai = SIMD_T::setzero_si();
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if (state.backendState.readViewportArrayIndex)
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{
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typename SIMD_T::Vec4 vpiAttrib[3];
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pa.Assemble(VERTEX_SGV_SLOT, vpiAttrib);
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vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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}
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if (state.backendState.readViewportArrayIndex) // VPAIOffsets are guaranteed 0-15 -- no OOB issues if they are offsets from 0
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{
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// OOB indices => forced to zero.
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typename SIMD_T::Integer vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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vpai = SIMD_T::max_epi32(SIMD_T::setzero_si(), vpai);
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vpai = SIMD_T::max_epi32(vpai, SIMD_T::setzero_si());
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typename SIMD_T::Integer vNumViewports = SIMD_T::set1_epi32(KNOB_NUM_VIEWPORTS_SCISSORS);
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typename SIMD_T::Integer vClearMask = SIMD_T::cmplt_epi32(vpai, vNumViewports);
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viewportIdx = SIMD_T::and_si(vClearMask, vpai);
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@@ -815,6 +821,7 @@ endBinTriangles:
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SIMD_T::store_si(reinterpret_cast<typename SIMD_T::Integer *>(aRTAI), SIMD_T::setzero_si());
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}
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// scan remaining valid triangles and bin each separately
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while (_BitScanForward(&triIndex, triMask))
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{
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@@ -1299,15 +1306,22 @@ void BinPointsImpl(
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const SWR_RASTSTATE& rastState = state.rastState;
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// Read back viewport index if required
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typename SIMD_T::Integer viewportIdx = SIMD_T::set1_epi32(0);
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typename SIMD_T::Integer viewportIdx = SIMD_T::setzero_si();
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typename SIMD_T::Vec4 vpiAttrib[1];
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typename SIMD_T::Integer vpai = SIMD_T::setzero_si();
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if (state.backendState.readViewportArrayIndex)
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{
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typename SIMD_T::Vec4 vpiAttrib[1];
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pa.Assemble(VERTEX_SGV_SLOT, vpiAttrib);
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vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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}
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if (state.backendState.readViewportArrayIndex) // VPAIOffsets are guaranteed 0-15 -- no OOB issues if they are offsets from 0
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{
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// OOB indices => forced to zero.
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typename SIMD_T::Integer vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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vpai = SIMD_T::max_epi32(SIMD_T::setzero_si(), vpai);
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vpai = SIMD_T::max_epi32(vpai, SIMD_T::setzero_si());
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typename SIMD_T::Integer vNumViewports = SIMD_T::set1_epi32(KNOB_NUM_VIEWPORTS_SCISSORS);
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typename SIMD_T::Integer vClearMask = SIMD_T::cmplt_epi32(vpai, vNumViewports);
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viewportIdx = SIMD_T::and_si(vClearMask, vpai);
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@@ -1626,15 +1640,22 @@ void SIMDCALL BinLinesImpl(
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typename SIMD_T::Float vRecipW[2] = { SIMD_T::set1_ps(1.0f), SIMD_T::set1_ps(1.0f) };
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typename SIMD_T::Integer viewportIdx = SIMD_T::set1_epi32(0);
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typename SIMD_T::Integer viewportIdx = SIMD_T::setzero_si();
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typename SIMD_T::Vec4 vpiAttrib[2];
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typename SIMD_T::Integer vpai = SIMD_T::setzero_si();
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if (state.backendState.readViewportArrayIndex)
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{
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typename SIMD_T::Vec4 vpiAttrib[2];
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pa.Assemble(VERTEX_SGV_SLOT, vpiAttrib);
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vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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}
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if (state.backendState.readViewportArrayIndex) // VPAIOffsets are guaranteed 0-15 -- no OOB issues if they are offsets from 0
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{
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// OOB indices => forced to zero.
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typename SIMD_T::Integer vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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vpai = SIMD_T::max_epi32(SIMD_T::setzero_si(), vpai);
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vpai = SIMD_T::max_epi32(vpai, SIMD_T::setzero_si());
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typename SIMD_T::Integer vNumViewports = SIMD_T::set1_epi32(KNOB_NUM_VIEWPORTS_SCISSORS);
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typename SIMD_T::Integer vClearMask = SIMD_T::cmplt_epi32(vpai, vNumViewports);
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viewportIdx = SIMD_T::and_si(vClearMask, vpai);
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@@ -641,7 +641,7 @@ public:
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}
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}
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PA_STATE_OPT clipPA(pDC, numEmittedPrims, reinterpret_cast<uint8_t *>(&transposedPrims[0]), numEmittedVerts, SWR_VTX_NUM_SLOTS, true, clipTopology);
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PA_STATE_OPT clipPA(pDC, numEmittedPrims, reinterpret_cast<uint8_t *>(&transposedPrims[0]), numEmittedVerts, SWR_VTX_NUM_SLOTS, true, NumVertsPerPrim, clipTopology);
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static const uint32_t primMaskMap[] = { 0x0, 0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f };
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@@ -687,15 +687,21 @@ public:
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UPDATE_STAT_FE(CInvocations, numInvoc);
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// Read back viewport index if required
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typename SIMD_T::Integer viewportIdx = SIMD_T::set1_epi32(0);
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typename SIMD_T::Integer viewportIdx = SIMD_T::setzero_si();
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typename SIMD_T::Vec4 vpiAttrib[NumVertsPerPrim];
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typename SIMD_T::Integer vpai = SIMD_T::setzero_si();
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if (state.backendState.readViewportArrayIndex)
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{
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typename SIMD_T::Vec4 vpiAttrib[NumVertsPerPrim];
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pa.Assemble(VERTEX_SGV_SLOT, vpiAttrib);
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vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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}
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if (state.backendState.readViewportArrayIndex) // VPAIOffsets are guaranteed 0-15 -- no OOB issues if they are offsets from 0
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{
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// OOB indices => forced to zero.
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typename SIMD_T::Integer vpai = SIMD_T::castps_si(vpiAttrib[0][VERTEX_SGV_VAI_COMP]);
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vpai = SIMD_T::max_epi32(vpai, SIMD_T::setzero_si());
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typename SIMD_T::Integer vNumViewports = SIMD_T::set1_epi32(KNOB_NUM_VIEWPORTS_SCISSORS);
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typename SIMD_T::Integer vClearMask = SIMD_T::cmplt_epi32(vpai, vNumViewports);
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@@ -951,7 +951,7 @@ static void GeometryShaderStage(
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}
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#if USE_SIMD16_FRONTEND
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PA_STATE_CUT gsPa(pDC, (uint8_t*)pGsBuffers->pGsTransposed, numEmittedVerts, pState->outputVertexSize, reinterpret_cast<simd16mask *>(pCutBuffer), numEmittedVerts, numAttribs, pState->outputTopology, processCutVerts);
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PA_STATE_CUT gsPa(pDC, (uint8_t*)pGsBuffers->pGsTransposed, numEmittedVerts, pState->outputVertexSize, reinterpret_cast<simd16mask *>(pCutBuffer), numEmittedVerts, numAttribs, pState->outputTopology, processCutVerts, pa.numVertsPerPrim);
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#else
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PA_STATE_CUT gsPa(pDC, (uint8_t*)pGsBuffers->pGsTransposed, numEmittedVerts, pState->outputVertexSize, pCutBuffer, numEmittedVerts, numAttribs, pState->outputTopology, processCutVerts);
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@@ -986,9 +986,10 @@ static void GeometryShaderStage(
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{
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#if USE_SIMD16_FRONTEND
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simd16scalari vPrimId = _simd16_set1_epi32(pPrimitiveId[inputPrim]);
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gsPa.useAlternateOffset = false;
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pfnClipFunc(pDC, gsPa, workerId, attrib_simd16, GenMask(gsPa.NumPrims()), vPrimId);
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{
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gsPa.useAlternateOffset = false;
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pfnClipFunc(pDC, gsPa, workerId, attrib_simd16, GenMask(gsPa.NumPrims()), vPrimId);
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}
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#else
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simdscalari vPrimId = _simd_set1_epi32(pPrimitiveId[inputPrim]);
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pfnClipFunc(pDC, gsPa, workerId, attrib, GenMask(gsPa.NumPrims()), vPrimId);
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@@ -1273,7 +1274,8 @@ static void TessellationStages(
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tsState.numDsOutputAttribs,
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tsData.ppIndices,
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tsData.NumPrimitives,
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tsState.postDSTopology);
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tsState.postDSTopology,
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numVertsPerPrim);
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while (tessPa.HasWork())
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{
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@@ -1498,7 +1500,8 @@ void ProcessDraw(
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}
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// choose primitive assembler
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PA_FACTORY<IsIndexedT, IsCutIndexEnabledT> paFactory(pDC, state.topology, work.numVerts, gpVertexStore, numVerts, state.frontendState.vsVertexSize);
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PA_FACTORY<IsIndexedT, IsCutIndexEnabledT> paFactory(pDC, state.topology, work.numVerts, gpVertexStore, numVerts, state.frontendState.vsVertexSize, GetNumVerts(state.topology, 1));
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PA_STATE& pa = paFactory.GetPA();
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#if USE_SIMD16_FRONTEND
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@@ -1727,9 +1730,10 @@ void ProcessDraw(
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if (HasRastT::value)
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{
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SWR_ASSERT(pDC->pState->pfnProcessPrims_simd16);
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pa.useAlternateOffset = false;
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pDC->pState->pfnProcessPrims_simd16(pDC, pa, workerId, prim_simd16, GenMask(numPrims), primID);
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{
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pa.useAlternateOffset = false;
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pDC->pState->pfnProcessPrims_simd16(pDC, pa, workerId, prim_simd16, GenMask(numPrims), primID);
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}
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}
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}
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}
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@@ -77,11 +77,12 @@ struct PA_STATE
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#if ENABLE_AVX512_SIMD16
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bool useAlternateOffset{ false };
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uint32_t numVertsPerPrim{ 0 };
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#endif
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PA_STATE() {}
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PA_STATE(DRAW_CONTEXT *in_pDC, uint8_t* in_pStreamBase, uint32_t in_streamSizeInVerts, uint32_t in_vertexStride) :
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pDC(in_pDC), pStreamBase(in_pStreamBase), streamSizeInVerts(in_streamSizeInVerts), vertexStride(in_vertexStride) {}
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PA_STATE(){}
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PA_STATE(DRAW_CONTEXT *in_pDC, uint8_t* in_pStreamBase, uint32_t in_streamSizeInVerts, uint32_t in_vertexStride, uint32_t in_numVertsPerPrim) :
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pDC(in_pDC), pStreamBase(in_pStreamBase), streamSizeInVerts(in_streamSizeInVerts), vertexStride(in_vertexStride), numVertsPerPrim(in_numVertsPerPrim) {}
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virtual bool HasWork() = 0;
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virtual simdvector& GetSimdVector(uint32_t index, uint32_t slot) = 0;
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@@ -165,7 +166,7 @@ struct PA_STATE_OPT : public PA_STATE
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PA_STATE_OPT() {}
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PA_STATE_OPT(DRAW_CONTEXT* pDC, uint32_t numPrims, uint8_t* pStream, uint32_t streamSizeInVerts,
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uint32_t vertexStride, bool in_isStreaming, PRIMITIVE_TOPOLOGY topo = TOP_UNKNOWN);
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uint32_t vertexStride, bool in_isStreaming, uint32_t numVertsPerPrim, PRIMITIVE_TOPOLOGY topo = TOP_UNKNOWN);
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bool HasWork()
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{
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@@ -430,8 +431,8 @@ struct PA_STATE_CUT : public PA_STATE
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PA_STATE_CUT() {}
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PA_STATE_CUT(DRAW_CONTEXT* pDC, uint8_t* in_pStream, uint32_t in_streamSizeInVerts, uint32_t in_vertexStride, SIMDMASK* in_pIndices, uint32_t in_numVerts,
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uint32_t in_numAttribs, PRIMITIVE_TOPOLOGY topo, bool in_processCutVerts)
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: PA_STATE(pDC, in_pStream, in_streamSizeInVerts, in_vertexStride)
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uint32_t in_numAttribs, PRIMITIVE_TOPOLOGY topo, bool in_processCutVerts, uint32_t in_numVertsPerPrim)
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: PA_STATE(pDC, in_pStream, in_streamSizeInVerts, in_vertexStride, in_numVertsPerPrim)
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{
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numVerts = in_streamSizeInVerts;
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numAttribs = in_numAttribs;
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@@ -1144,9 +1145,10 @@ struct PA_TESS : PA_STATE
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uint32_t in_numAttributes,
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uint32_t* (&in_ppIndices)[3],
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uint32_t in_numPrims,
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PRIMITIVE_TOPOLOGY in_binTopology) :
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PRIMITIVE_TOPOLOGY in_binTopology,
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uint32_t numVertsPerPrim) :
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PA_STATE(in_pDC, nullptr, 0, in_vertexStride),
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PA_STATE(in_pDC, nullptr, 0, in_vertexStride, numVertsPerPrim),
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m_pVertexData(in_pVertData),
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m_attributeStrideInVectors(in_attributeStrideInVectors),
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m_numAttributes(in_numAttributes),
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@@ -1416,7 +1418,7 @@ private:
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template <typename IsIndexedT, typename IsCutIndexEnabledT>
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struct PA_FACTORY
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{
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PA_FACTORY(DRAW_CONTEXT* pDC, PRIMITIVE_TOPOLOGY in_topo, uint32_t numVerts, PA_STATE::SIMDVERTEX *pVertexStore, uint32_t vertexStoreSize, uint32_t vertexStride) : topo(in_topo)
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PA_FACTORY(DRAW_CONTEXT* pDC, PRIMITIVE_TOPOLOGY in_topo, uint32_t numVerts, PA_STATE::SIMDVERTEX *pVertexStore, uint32_t vertexStoreSize, uint32_t vertexStride, uint32_t numVertsPerPrim) : topo(in_topo)
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{
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#if KNOB_ENABLE_CUT_AWARE_PA == TRUE
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const API_STATE& state = GetApiState(pDC);
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@@ -1433,14 +1435,14 @@ struct PA_FACTORY
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uint32_t numAttribs = state.feNumAttributes;
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new (&this->paCut) PA_STATE_CUT(pDC, reinterpret_cast<uint8_t *>(pVertexStore), vertexStoreSize * PA_STATE::SIMD_WIDTH,
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vertexStride, &this->indexStore[0], numVerts, numAttribs, state.topology, false);
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vertexStride, &this->indexStore[0], numVerts, numAttribs, state.topology, false, numVertsPerPrim);
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cutPA = true;
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}
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else
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#endif
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{
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uint32_t numPrims = GetNumPrims(in_topo, numVerts);
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new (&this->paOpt) PA_STATE_OPT(pDC, numPrims, reinterpret_cast<uint8_t *>(pVertexStore), vertexStoreSize * PA_STATE::SIMD_WIDTH, vertexStride, false);
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new (&this->paOpt) PA_STATE_OPT(pDC, numPrims, reinterpret_cast<uint8_t *>(pVertexStore), vertexStoreSize * PA_STATE::SIMD_WIDTH, vertexStride, false, numVertsPerPrim);
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cutPA = false;
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}
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@@ -2588,8 +2588,8 @@ void PaRectListSingle0(
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}
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PA_STATE_OPT::PA_STATE_OPT(DRAW_CONTEXT *in_pDC, uint32_t in_numPrims, uint8_t* pStream, uint32_t in_streamSizeInVerts,
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uint32_t in_vertexStride, bool in_isStreaming, PRIMITIVE_TOPOLOGY topo) :
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PA_STATE(in_pDC, pStream, in_streamSizeInVerts, in_vertexStride), numPrims(in_numPrims), numPrimsComplete(0), numSimdPrims(0),
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uint32_t in_vertexStride, bool in_isStreaming, uint32_t numVertsPerPrim, PRIMITIVE_TOPOLOGY topo) :
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PA_STATE(in_pDC, pStream, in_streamSizeInVerts, in_vertexStride, numVertsPerPrim), numPrims(in_numPrims), numPrimsComplete(0), numSimdPrims(0),
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cur(0), prev(0), first(0), counter(0), reset(false), pfnPaFunc(nullptr), isStreaming(in_isStreaming)
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{
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const API_STATE& state = GetApiState(pDC);
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