AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

gallium/radeon: merge BO read/write usage flags with priority flags

Browse Source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
This commit is contained in:
Marek Olšák
2021-10-21 23:17:03 -04:00
committed by Marge Bot
parent 90ff5ef5c0
commit 61bd8ec043
49 changed files with 286 additions and 310 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/r300/r300_emit.c
+28 -27
View File
@@ -1323,31 +1323,31 @@ validate:
tex = r300_resource(fb->cbufs[i]->texture);
assert(tex && tex->buf && "cbuf is marked, but NULL!");
r300->rws->cs_add_buffer(&r300->cs, tex->buf,
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED,
r300_surface(fb->cbufs[i])->domain,
tex->b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED |
(tex->b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER),
r300_surface(fb->cbufs[i])->domain);
}
/* ...depth buffer... */
if (fb->zsbuf) {
tex = r300_resource(fb->zsbuf->texture);
assert(tex && tex->buf && "zsbuf is marked, but NULL!");
r300->rws->cs_add_buffer(&r300->cs, tex->buf,
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED,
r300_surface(fb->zsbuf)->domain,
tex->b.nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED |
(tex->b.nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER),
r300_surface(fb->zsbuf)->domain);
}
}
/* The AA resolve buffer. */
if (r300->aa_state.dirty) {
if (aa->dest) {
r300->rws->cs_add_buffer(&r300->cs, aa->dest->buf,
RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED,
aa->dest->domain,
RADEON_PRIO_COLOR_BUFFER);
RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED |
RADEON_PRIO_COLOR_BUFFER,
aa->dest->domain);
}
}
if (r300->textures_state.dirty) {
@@ -1359,22 +1359,23 @@ validate:
tex = r300_resource(texstate->sampler_views[i]->base.texture);
r300->rws->cs_add_buffer(&r300->cs, tex->buf,
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
tex->domain, RADEON_PRIO_SAMPLER_TEXTURE);
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
RADEON_PRIO_SAMPLER_TEXTURE,
tex->domain);
}
}
/* ...occlusion query buffer... */
if (r300->query_current)
r300->rws->cs_add_buffer(&r300->cs, r300->query_current->buf,
RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED,
RADEON_DOMAIN_GTT,
RADEON_PRIO_QUERY);
RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED |
RADEON_PRIO_QUERY,
RADEON_DOMAIN_GTT);
/* ...vertex buffer for SWTCL path... */
if (r300->vbo)
r300->rws->cs_add_buffer(&r300->cs, r300->vbo,
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
RADEON_DOMAIN_GTT,
RADEON_PRIO_VERTEX_BUFFER);
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
RADEON_PRIO_VERTEX_BUFFER,
RADEON_DOMAIN_GTT);
/* ...vertex buffers for HWTCL path... */
if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
@@ -1388,17 +1389,17 @@ validate:
continue;
r300->rws->cs_add_buffer(&r300->cs, r300_resource(buf)->buf,
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
r300_resource(buf)->domain,
RADEON_PRIO_SAMPLER_BUFFER);
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
RADEON_PRIO_SAMPLER_BUFFER,
r300_resource(buf)->domain);
}
}
/* ...and index buffer for HWTCL path. */
if (index_buffer)
r300->rws->cs_add_buffer(&r300->cs, r300_resource(index_buffer)->buf,
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
r300_resource(index_buffer)->domain,
RADEON_PRIO_INDEX_BUFFER);
RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
RADEON_PRIO_INDEX_BUFFER,
r300_resource(index_buffer)->domain);
/* Now do the validation (flush is called inside cs_validate on failure). */
if (!r300->rws->cs_validate(&r300->cs)) {
src/gallium/drivers/r600/evergreen_compute.c
+2 -2
View File
@@ -687,7 +687,7 @@ static void compute_setup_cbs(struct r600_context *rctx)
struct r600_surface *cb = (struct r600_surface*)rctx->framebuffer.state.cbufs[i];
unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
(struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RW_BUFFER);
radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7);
@@ -918,7 +918,7 @@ void evergreen_emit_cs_shader(struct r600_context *rctx,
radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
code_bo, RADEON_USAGE_READ,
code_bo, RADEON_USAGE_READ |
RADEON_PRIO_SHADER_BINARY));
}
src/gallium/drivers/r600/evergreen_hw_context.c
+3 -3
View File
@@ -64,8 +64,8 @@ void evergreen_dma_copy_buffer(struct r600_context *rctx,
for (i = 0; i < ncopy; i++) {
csize = size < EG_DMA_COPY_MAX_SIZE ? size : EG_DMA_COPY_MAX_SIZE;
/* emit reloc before writing cs so that cs is always in consistent state */
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ, 0);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE);
radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize));
radeon_emit(cs, dst_offset & 0xffffffff);
radeon_emit(cs, src_offset & 0xffffffff);
@@ -123,7 +123,7 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
/* This must be done after r600_need_cs_space. */
reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
(struct r600_resource*)dst, RADEON_USAGE_WRITE,
(struct r600_resource*)dst, RADEON_USAGE_WRITE |
RADEON_PRIO_CP_DMA);
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
src/gallium/drivers/r600/evergreen_state.c
+26 -27
View File
@@ -1736,13 +1736,13 @@ static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_at
reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
resource,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RW_BUFFER);
immed_reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
resource->immed_buffer,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RW_BUFFER);
if (pkt_flags)
@@ -1866,15 +1866,14 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
(struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE,
tex->resource.b.b.nr_samples > 1 ?
RADEON_USAGE_READWRITE |
(tex->resource.b.b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
RADEON_PRIO_COLOR_BUFFER));
if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
tex->cmask_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_SEPARATE_META);
tex->cmask_buffer, RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
} else {
cmask_reloc = reloc;
}
@@ -1925,10 +1924,10 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
(struct r600_resource*)state->zsbuf->texture,
RADEON_USAGE_READWRITE,
zb->base.texture->nr_samples > 1 ?
RADEON_USAGE_READWRITE |
(zb->base.texture->nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
RADEON_PRIO_DEPTH_BUFFER));
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
@@ -2063,7 +2062,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom
radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc_idx);
} else {
@@ -2165,7 +2164,7 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER));
}
state->dirty_mask = 0;
}
@@ -2211,7 +2210,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
pkt_flags);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
}
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
@@ -2237,7 +2236,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
dirty_mask &= ~(1 << buffer_index);
}
@@ -2356,7 +2355,7 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx,
radeon_emit_array(cs, rview->tex_resource_words, 8);
reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
r600_get_sampler_view_priority(rview->tex_resource));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
radeon_emit(cs, reloc);
@@ -2561,7 +2560,7 @@ static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct
(shader->buffer->gpu_address + shader->offset) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_SHADER_BINARY));
}
@@ -2685,7 +2684,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
rbuffer->gpu_address >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
@@ -2695,7 +2694,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
rbuffer->gpu_address >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
@@ -3867,9 +3866,9 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
size = (cheight * pitch) / 4;
/* emit reloc before writing cs so that cs is always in consistent state */
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
RADEON_USAGE_READ, 0);
RADEON_USAGE_READ);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
RADEON_USAGE_WRITE, 0);
RADEON_USAGE_WRITE);
radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
radeon_emit(cs, base >> 8);
radeon_emit(cs, (detile << 31) | (array_mode << 27) |
@@ -4784,12 +4783,12 @@ void eg_trace_emit(struct r600_context *rctx)
/* This must be done after r600_need_cs_space. */
reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
(struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE,
(struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE |
RADEON_PRIO_CP_DMA);
rctx->trace_id++;
radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
RADEON_USAGE_READWRITE, RADEON_PRIO_FENCE_TRACE);
RADEON_USAGE_READWRITE | RADEON_PRIO_FENCE_TRACE);
radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
radeon_emit(cs, rctx->trace_buf->gpu_address);
radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
@@ -4809,7 +4808,7 @@ static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
resource,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_SHADER_RW_BUFFER);
uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
@@ -4834,7 +4833,7 @@ static void evergreen_emit_event_write_eos(struct r600_context *rctx,
uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
resource,
RADEON_USAGE_WRITE,
RADEON_USAGE_WRITE |
RADEON_PRIO_SHADER_RW_BUFFER);
uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
@@ -4860,7 +4859,7 @@ static void cayman_emit_event_write_eos(struct r600_context *rctx,
uint32_t event = EVENT_TYPE_PS_DONE;
uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
resource,
RADEON_USAGE_WRITE,
RADEON_USAGE_WRITE |
RADEON_PRIO_SHADER_RW_BUFFER);
uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
@@ -4885,7 +4884,7 @@ static void cayman_write_count_to_gds(struct r600_context *rctx,
struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
resource,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_SHADER_RW_BUFFER);
uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
@@ -5010,7 +5009,7 @@ void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
++rctx->append_fence_id;
reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
r600_resource(rctx->append_fence),
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RW_BUFFER);
dst_offset = r600_resource(rctx->append_fence)->gpu_address;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
src/gallium/drivers/r600/r600_buffer_common.c
+2 -2
View File
@@ -33,7 +33,7 @@
bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
struct pb_buffer *buf,
enum radeon_bo_usage usage)
unsigned usage)
{
if (ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, buf, usage)) {
return true;
@@ -49,7 +49,7 @@ void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
struct r600_resource *resource,
unsigned usage)
{
enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
unsigned rusage = RADEON_USAGE_READWRITE;
bool busy = false;
assert(!(resource->flags & RADEON_FLAG_SPARSE));
src/gallium/drivers/r600/r600_cs.h
+7 -10
View File
@@ -69,14 +69,13 @@ radeon_cs_memory_below_limit(struct r600_common_screen *screen,
static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
struct r600_ring *ring,
struct r600_resource *rbo,
enum radeon_bo_usage usage,
unsigned priority)
unsigned usage)
{
assert(usage);
return rctx->ws->cs_add_buffer(
&ring->cs, rbo->buf,
(enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
rbo->domains, priority) * 4;
usage | RADEON_USAGE_SYNCHRONIZED,
rbo->domains) * 4;
}
/**
@@ -100,8 +99,7 @@ static inline unsigned
radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
struct r600_ring *ring,
struct r600_resource *rbo,
enum radeon_bo_usage usage,
unsigned priority,
unsigned usage,
bool check_mem)
{
if (check_mem &&
@@ -110,17 +108,16 @@ radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
rctx->gtt + rbo->gart_usage))
ring->flush(rctx, PIPE_FLUSH_ASYNC, NULL);
return radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
return radeon_add_to_buffer_list(rctx, ring, rbo, usage);
}
static inline void r600_emit_reloc(struct r600_common_context *rctx,
struct r600_ring *ring, struct r600_resource *rbo,
enum radeon_bo_usage usage,
unsigned priority)
unsigned usage)
{
struct radeon_cmdbuf *cs = &ring->cs;
bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_has_virtual_memory;
unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage);
if (!has_vm) {
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
src/gallium/drivers/r600/r600_hw_context.c
+5 -5
View File
@@ -460,7 +460,7 @@ void r600_emit_pfp_sync_me(struct r600_context *rctx)
}
reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, buf,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_FENCE_TRACE);
va = buf->gpu_address + offset;
@@ -543,9 +543,9 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
/* This must be done after r600_need_cs_space. */
src_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)src,
RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
RADEON_USAGE_READ | RADEON_PRIO_CP_DMA);
dst_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)dst,
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA);
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */
@@ -602,8 +602,8 @@ void r600_dma_copy_buffer(struct r600_context *rctx,
for (i = 0; i < ncopy; i++) {
csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
/* emit reloc before writing cs so that cs is always in consistent state */
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ, 0);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE, 0);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE);
radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize));
radeon_emit(cs, dst_offset & 0xfffffffc);
radeon_emit(cs, src_offset & 0xfffffffc);
src/gallium/drivers/r600/r600_pipe_common.c
+4 -4
View File
@@ -92,7 +92,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
radeon_emit(cs, 0); /* unused */
if (buf)
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE |
RADEON_PRIO_QUERY);
}
@@ -121,7 +121,7 @@ void r600_gfx_wait_fence(struct r600_common_context *ctx,
radeon_emit(cs, 4); /* poll interval */
if (buf)
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ |
RADEON_PRIO_QUERY);
}
@@ -287,10 +287,10 @@ void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
if (ctx->screen->info.r600_has_virtual_memory) {
if (dst)
radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
RADEON_USAGE_WRITE, 0);
RADEON_USAGE_WRITE);
if (src)
radeon_add_to_buffer_list(ctx, &ctx->dma, src,
RADEON_USAGE_READ, 0);
RADEON_USAGE_READ);
}
/* this function is called before all DMA calls, so increment this. */
src/gallium/drivers/r600/r600_pipe_common.h
+1 -1
View File
@@ -628,7 +628,7 @@ struct r600_common_context {
/* r600_buffer_common.c */
bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
struct pb_buffer *buf,
enum radeon_bo_usage usage);
unsigned usage);
void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
struct r600_resource *resource,
unsigned usage);
src/gallium/drivers/r600/r600_query.c
+4 -4
View File
@@ -766,7 +766,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
default:
assert(0);
}
r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE |
RADEON_PRIO_QUERY);
}
@@ -859,7 +859,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
default:
assert(0);
}
r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE |
RADEON_PRIO_QUERY);
if (fence_va)
@@ -905,7 +905,7 @@ static void emit_set_predicate(struct r600_common_context *ctx,
radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
radeon_emit(cs, va);
radeon_emit(cs, op | ((va >> 32) & 0xFF));
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ |
RADEON_PRIO_QUERY);
}
@@ -1904,7 +1904,7 @@ void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
radeon_emit(cs, buffer->gpu_address >> 32);
r600_emit_reloc(ctx, &ctx->gfx, buffer,
RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
/* analyze results */
results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_MAP_READ);
src/gallium/drivers/r600/r600_state.c
+22 -22
View File
@@ -1387,10 +1387,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
(struct r600_resource*)cb[i]->base.texture,
RADEON_USAGE_READWRITE,
cb[i]->base.texture->nr_samples > 1 ?
RADEON_USAGE_READWRITE |
(cb[i]->base.texture->nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
RADEON_PRIO_COLOR_BUFFER));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
@@ -1400,10 +1400,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
cb[i]->cb_buffer_fmask,
RADEON_USAGE_READWRITE,
cb[i]->base.texture->nr_samples > 1 ?
RADEON_USAGE_READWRITE |
(cb[i]->base.texture->nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
RADEON_PRIO_COLOR_BUFFER));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
@@ -1413,10 +1413,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
cb[i]->cb_buffer_cmask,
RADEON_USAGE_READWRITE,
cb[i]->base.texture->nr_samples > 1 ?
RADEON_USAGE_READWRITE |
(cb[i]->base.texture->nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
RADEON_PRIO_COLOR_BUFFER));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
}
@@ -1452,10 +1452,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx,
(struct r600_resource*)state->zsbuf->texture,
RADEON_USAGE_READWRITE,
surf->base.texture->nr_samples > 1 ?
RADEON_USAGE_READWRITE |
(surf->base.texture->nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
RADEON_PRIO_DEPTH_BUFFER));
radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
@@ -1561,7 +1561,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom
radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc_idx);
} else {
@@ -1695,7 +1695,7 @@ static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER));
}
}
@@ -1727,7 +1727,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
}
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
@@ -1744,7 +1744,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
dirty_mask &= ~(1 << buffer_index);
}
@@ -1795,7 +1795,7 @@ static void r600_emit_sampler_views(struct r600_context *rctx,
radeon_emit_array(cs, rview->tex_resource_words, 7);
reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
r600_get_sampler_view_priority(rview->tex_resource));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc);
@@ -1920,7 +1920,7 @@ static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600
radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_SHADER_BINARY));
}
@@ -1974,7 +1974,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
@@ -1983,7 +1983,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
@@ -2929,8 +2929,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
cheight = cheight > copy_height ? copy_height : cheight;
size = (cheight * pitch) / 4;
/* emit reloc before writing cs so that cs is always in consistent state */
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ, 0);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE, 0);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ);
radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE);
radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
radeon_emit(cs, base >> 8);
radeon_emit(cs, (detile << 31) | (array_mode << 27) |
src/gallium/drivers/r600/r600_state_common.c
+6 -6
View File
@@ -1736,7 +1736,7 @@ void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SCRATCH_BUFFER));
radeon_set_context_reg(cs, item_size_reg, itemsize);
radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
@@ -2360,7 +2360,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
(struct r600_resource*)indirect->buffer,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_DRAW_INDIRECT));
}
@@ -2389,7 +2389,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
(struct r600_resource*)indexbuf,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_INDEX_BUFFER));
}
else {
@@ -2402,7 +2402,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
(struct r600_resource*)indexbuf,
RADEON_USAGE_READ,
RADEON_USAGE_READ |
RADEON_PRIO_INDEX_BUFFER));
radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
@@ -2429,7 +2429,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
t->buf_filled_size, RADEON_USAGE_READ,
t->buf_filled_size, RADEON_USAGE_READ |
RADEON_PRIO_SO_FILLED_SIZE));
}
@@ -2637,7 +2637,7 @@ void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
r600_emit_command_buffer(cs, &shader->command_buffer);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY));
}
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
src/gallium/drivers/r600/r600_streamout.c
+4 -4
View File
@@ -204,7 +204,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
radeon_emit(cs, va >> 8); /* BUFFER_BASE */
r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
RADEON_USAGE_WRITE | RADEON_PRIO_SHADER_RW_BUFFER);
/* R7xx requires this packet after updating BUFFER_BASE.
* Without this, R7xx locks up. */
@@ -214,7 +214,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
radeon_emit(cs, va >> 8);
r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
RADEON_USAGE_WRITE | RADEON_PRIO_SHADER_RW_BUFFER);
}
if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
@@ -231,7 +231,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
radeon_emit(cs, va >> 32); /* src address hi */
r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE);
RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
} else {
/* Start from the beginning. */
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
@@ -275,7 +275,7 @@ void r600_emit_streamout_end(struct r600_common_context *rctx)
radeon_emit(cs, 0); /* unused */
r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
RADEON_USAGE_WRITE, RADEON_PRIO_SO_FILLED_SIZE);
RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);
/* Zero the buffer size. The counters (primitives generated,
* primitives emitted) may be enabled even if there is not
src/gallium/drivers/r600/radeon_uvd.c
+2 -2
View File
@@ -115,12 +115,12 @@ static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
/* send a command to the VCPU through the GPCOM registers */
static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
struct pb_buffer* buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
unsigned usage, enum radeon_bo_domain domain)
{
int reloc_idx;
reloc_idx = dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
domain);
if (!dec->use_legacy) {
uint64_t addr;
addr = dec->ws->buffer_get_virtual_address(buf);
src/gallium/drivers/r600/radeon_vce.c
+2 -2
View File
@@ -513,13 +513,13 @@ bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
* Add the buffer as relocation to the current command submission
*/
void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
unsigned usage, enum radeon_bo_domain domain,
signed offset)
{
int reloc_idx;
reloc_idx = enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
domain);
if (enc->use_vm) {
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);
src/gallium/drivers/r600/radeon_vce.h
+1 -1
View File
@@ -431,7 +431,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
unsigned usage, enum radeon_bo_domain domain,
signed offset);
/* init vce fw 40.2.2 specific callbacks */
src/gallium/drivers/radeon/radeon_uvd.c
+2 -2
View File
@@ -108,11 +108,11 @@ static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
/* send a command to the VCPU through the GPCOM registers */
static void send_cmd(struct ruvd_decoder *dec, unsigned cmd, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
unsigned usage, enum radeon_bo_domain domain)
{
int reloc_idx;
reloc_idx = dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
reloc_idx = dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
if (!dec->use_legacy) {
uint64_t addr;
addr = dec->ws->buffer_get_virtual_address(buf);
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+2 -2
View File
@@ -54,10 +54,10 @@
static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
static void radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
unsigned usage, enum radeon_bo_domain domain,
signed offset)
{
enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);
addr = addr + offset;
src/gallium/drivers/radeon/radeon_vce.c
+2 -2
View File
@@ -536,12 +536,12 @@ bool si_vce_is_fw_version_supported(struct si_screen *sscreen)
/**
* Add the buffer as relocation to the current command submission
*/
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, enum radeon_bo_usage usage,
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, unsigned usage,
enum radeon_bo_domain domain, signed offset)
{
int reloc_idx;
reloc_idx = enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
reloc_idx = enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
if (enc->use_vm) {
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);
src/gallium/drivers/radeon/radeon_vce.h
+1 -1
View File
@@ -432,7 +432,7 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
bool si_vce_is_fw_version_supported(struct si_screen *sscreen);
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, enum radeon_bo_usage usage,
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, unsigned usage,
enum radeon_bo_domain domain, signed offset);
/* init vce fw 40.2.2 specific callbacks */
src/gallium/drivers/radeon/radeon_vcn_dec.c
+3 -3
View File
@@ -1414,7 +1414,7 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn
}
dec->ws->cs_add_buffer(&dec->cs, dpb->dpb.res->buf,
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED, RADEON_DOMAIN_VRAM, 0);
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED, RADEON_DOMAIN_VRAM);
addr = dec->ws->buffer_get_virtual_address(dpb->dpb.res->buf);
dynamic_dpb_t2->dpbCurrLo = addr;
dynamic_dpb_t2->dpbCurrHi = addr >> 32;
@@ -1863,11 +1863,11 @@ static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
/* send a command to the VCPU through the GPCOM registers */
static void send_cmd(struct radeon_decoder *dec, unsigned cmd, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
unsigned usage, enum radeon_bo_domain domain)
{
uint64_t addr;
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
+8 -8
View File
@@ -63,7 +63,7 @@ static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg, unsigned cond
/* send a bitstream buffer command */
static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
unsigned usage, enum radeon_bo_domain domain)
{
uint64_t addr;
@@ -85,7 +85,7 @@ static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer *buf
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
@@ -106,7 +106,7 @@ static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer *buf
/* send a target buffer command */
static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
unsigned usage, enum radeon_bo_domain domain)
{
uint64_t addr;
@@ -117,7 +117,7 @@ static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer *buf, u
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
@@ -185,7 +185,7 @@ static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer *buf, u
/* send a bitstream buffer command */
static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buffer *buf,
uint32_t off, enum radeon_bo_usage usage,
uint32_t off, unsigned usage,
enum radeon_bo_domain domain)
{
uint64_t addr;
@@ -205,7 +205,7 @@ static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buff
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10));
set_reg_jpeg(dec, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
@@ -225,7 +225,7 @@ static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buff
/* send a target buffer command */
static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
unsigned usage, enum radeon_bo_domain domain)
{
uint64_t addr;
@@ -236,7 +236,7 @@ static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer
set_reg_jpeg(dec, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
src/gallium/drivers/radeon/radeon_vcn_enc.c
+2 -2
View File
@@ -478,9 +478,9 @@ error:
}
void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset)
unsigned usage, enum radeon_bo_domain domain, signed offset)
{
enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);
addr = addr + offset;
src/gallium/drivers/radeon/radeon_vcn_enc.h
+1 -1
View File
@@ -556,7 +556,7 @@ struct radeon_encoder {
};
void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset);
unsigned usage, enum radeon_bo_domain domain, signed offset);
void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
src/gallium/drivers/radeon/radeon_winsys.h
+21 -24
View File
@@ -78,23 +78,6 @@ enum radeon_bo_flag
RADEON_FLAG_DRIVER_INTERNAL = (1 << 9),
};
enum radeon_bo_usage
{ /* bitfield */
RADEON_USAGE_READ = 2,
RADEON_USAGE_WRITE = 4,
RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
/* The winsys ensures that the CS submission will be scheduled after
* previously flushed CSs referencing this BO in a conflicting way.
*/
RADEON_USAGE_SYNCHRONIZED = 8,
/* When used, an implicit sync is done to make sure a compute shader
* will read the written values from a previous draw.
*/
RADEON_USAGE_NEEDS_IMPLICIT_SYNC = 16,
};
enum radeon_map_flags
{
/* Indicates that the caller will unmap the buffer.
@@ -171,6 +154,23 @@ enum radeon_value_id
#define RADEON_PRIO_SHADER_RINGS (1 << 22)
#define RADEON_PRIO_SCRATCH_BUFFER (1 << 23)
#define RADEON_ALL_PRIORITIES (RADEON_USAGE_READ - 1)
/* Upper bits of priorities are used by usage flags. */
#define RADEON_USAGE_READ (1 << 28)
#define RADEON_USAGE_WRITE (1 << 29)
#define RADEON_USAGE_READWRITE (RADEON_USAGE_READ | RADEON_USAGE_WRITE)
/* The winsys ensures that the CS submission will be scheduled after
* previously flushed CSs referencing this BO in a conflicting way.
*/
#define RADEON_USAGE_SYNCHRONIZED (1 << 30)
/* When used, an implicit sync is done to make sure a compute shader
* will read the written values from a previous draw.
*/
#define RADEON_USAGE_NEEDS_IMPLICIT_SYNC (1u << 31)
struct winsys_handle;
struct radeon_winsys_ctx;
@@ -333,7 +333,7 @@ struct radeon_winsys {
* is idle.
*/
bool (*buffer_wait)(struct radeon_winsys *ws, struct pb_buffer *buf,
uint64_t timeout, enum radeon_bo_usage usage);
uint64_t timeout, unsigned usage);
/**
* Return buffer metadata.
@@ -512,15 +512,12 @@ struct radeon_winsys {
*
* \param cs Command stream
* \param buf Buffer
* \param usage Whether the buffer is used for read and/or write.
* \param usage Usage
* \param domain Bitmask of the RADEON_DOMAIN_* flags.
* \param priority A higher number means a greater chance of being
* placed in the requested domain. 15 is the maximum.
* \return Buffer index.
*/
unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
unsigned priority);
unsigned usage, enum radeon_bo_domain domain);
/**
* Return the index of an already-added buffer.
@@ -594,7 +591,7 @@ struct radeon_winsys {
* \param buf A winsys buffer.
*/
bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
enum radeon_bo_usage usage);
unsigned usage);
/**
* Request access to a feature for a command stream.
src/gallium/drivers/radeonsi/si_buffer.c
+1 -1
View File
@@ -31,7 +31,7 @@
#include <stdio.h>
bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
enum radeon_bo_usage usage)
unsigned usage)
{
return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage);
}
src/gallium/drivers/radeonsi/si_compute.c
+12 -12
View File
@@ -523,8 +523,8 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute
sctx->scratch_waves, config->scratch_bytes_per_wave,
config->scratch_bytes_per_wave * sctx->scratch_waves);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->scratch_bo,
RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
}
shader_va = shader->bo->gpu_address + offset;
@@ -534,8 +534,8 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute
shader_va += sizeof(amd_kernel_code_t);
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo, RADEON_USAGE_READ,
RADEON_PRIO_SHADER_BINARY);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo,
RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
radeon_begin(cs);
radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
@@ -654,8 +654,8 @@ static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_
fprintf(stderr, "Error: Failed to allocate dispatch "
"packet.");
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ,
RADEON_PRIO_CONST_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf,
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
@@ -711,8 +711,8 @@ static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_co
COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer, RADEON_USAGE_READ,
RADEON_PRIO_CONST_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer,
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
si_resource_reference(&input_buffer, NULL);
@@ -823,8 +823,8 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
if (info->indirect) {
uint64_t base_va = si_resource(info->indirect)->gpu_address;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ,
RADEON_PRIO_DRAW_INDIRECT);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect),
RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
radeon_emit(PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
radeon_emit(1);
@@ -976,8 +976,8 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
if (!buffer) {
continue;
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer,
RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RW_BUFFER);
}
/* Registers that are not read from memory should be set before this: */
src/gallium/drivers/radeonsi/si_compute_blit.c
+1 -1
View File
@@ -60,7 +60,7 @@ unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
}
static bool si_is_buffer_idle(struct si_context *sctx, struct si_resource *buf,
enum radeon_bo_usage usage)
unsigned usage)
{
return !si_cs_is_buffer_referenced(sctx, buf->buf, usage) &&
sctx->ws->buffer_wait(sctx->ws, buf->buf, 0, usage);
src/gallium/drivers/radeonsi/si_cp_dma.c
+7 -7
View File
@@ -157,11 +157,11 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
/* This must be done after need_cs_space. */
if (dst)
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), RADEON_USAGE_WRITE,
RADEON_PRIO_CP_DMA);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst),
RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA);
if (src)
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), RADEON_USAGE_READ,
RADEON_PRIO_CP_DMA);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src),
RADEON_USAGE_READ | RADEON_PRIO_CP_DMA);
/* Flush the caches for the first copy only.
* Also wait for the previous CP DMA operations.
@@ -493,7 +493,7 @@ void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned
if (sctx->chip_class == GFX6 && dst_sel == V_370_MEM)
dst_sel = V_370_MEM_GRBM;
radeon_add_to_buffer_list(sctx, cs, buf, RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
radeon_add_to_buffer_list(sctx, cs, buf, RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA);
uint64_t va = buf->gpu_address + offset;
radeon_begin(cs);
@@ -511,10 +511,10 @@ void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned
{
/* cs can point to the compute IB, which has the buffer list in gfx_cs. */
if (dst) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dst, RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dst, RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA);
}
if (src) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, src, RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, src, RADEON_USAGE_READ | RADEON_PRIO_CP_DMA);
}
uint64_t dst_va = (dst ? dst->gpu_address : 0ull) + dst_offset;
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
+1 -1
View File
@@ -175,7 +175,7 @@ void si_init_cp_reg_shadowing(struct si_context *sctx)
/* Initialize shadowed registers as follows. */
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowed_regs,
RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
RADEON_USAGE_READWRITE | RADEON_PRIO_DESCRIPTORS);
si_pm4_emit(sctx, shadowing_preamble);
ac_emulate_clear_state(&sctx->screen->info, &sctx->gfx_cs, si_set_context_reg_array);
si_pm4_emit(sctx, sctx->cs_preamble_state);
src/gallium/drivers/radeonsi/si_descriptors.c
+24 -24
View File
@@ -163,8 +163,8 @@ static bool si_upload_descriptors(struct si_context *sctx, struct si_descriptors
util_memcpy_cpu_to_le32(ptr, (char *)desc->list + first_slot_offset, upload_size);
desc->gpu_list = ptr - first_slot_offset / 4;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer,
RADEON_USAGE_READ | RADEON_PRIO_DESCRIPTORS);
/* The shader pointer should point to slot 0. */
buffer_offset -= first_slot_offset;
@@ -182,8 +182,8 @@ si_add_descriptors_to_bo_list(struct si_context *sctx, struct si_descriptors *de
if (!desc->buffer)
return;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer,
RADEON_USAGE_READ | RADEON_PRIO_DESCRIPTORS);
}
/* SAMPLER VIEWS */
@@ -215,7 +215,7 @@ static void si_release_sampler_views(struct si_samplers *samplers)
}
static void si_sampler_view_add_buffer(struct si_context *sctx, struct pipe_resource *resource,
enum radeon_bo_usage usage, bool is_stencil_sampler,
unsigned usage, bool is_stencil_sampler,
bool check_mem)
{
struct si_texture *tex = (struct si_texture *)resource;
@@ -230,7 +230,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx, struct pipe_reso
tex = tex->flushed_depth_texture;
priority = si_get_sampler_view_priority(&tex->buffer);
radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, check_mem);
radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage | priority, check_mem);
}
static void si_sampler_views_begin_new_cs(struct si_context *sctx, struct si_samplers *samplers)
@@ -963,8 +963,8 @@ void si_update_ps_colorbuf0_slot(struct si_context *sctx)
si_set_shader_image_desc(sctx, &view, true, desc, desc + 8);
pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READ,
RADEON_PRIO_SHADER_RW_IMAGE);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer,
RADEON_USAGE_READ | RADEON_PRIO_SHADER_RW_IMAGE);
buffers->enabled_mask |= 1llu << slot;
} else {
/* Clear the descriptor. */
@@ -1078,8 +1078,8 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
radeon_add_to_buffer_list(
sctx, &sctx->gfx_cs, si_resource(buffers->buffers[i]),
buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf);
(buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ) |
(i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf));
}
}
@@ -1136,13 +1136,13 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs,
si_resource(sctx->vertex_buffer[vb].buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
}
if (!sctx->vb_descriptors_buffer)
return;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->vb_descriptors_buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->vb_descriptors_buffer,
RADEON_USAGE_READ | RADEON_PRIO_DESCRIPTORS);
}
/* CONSTANT BUFFERS */
@@ -1210,8 +1210,8 @@ static void si_set_constant_buffer(struct si_context *sctx, struct si_buffer_res
buffers->buffers[slot] = buffer;
buffers->offsets[slot] = buffer_offset;
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
buffers->priority_constbuf, true);
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
RADEON_USAGE_READ | buffers->priority_constbuf, true);
buffers->enabled_mask |= 1llu << slot;
} else {
/* Clear the descriptor. Only 3 dwords are cleared. The 4th dword is immutable. */
@@ -1356,7 +1356,7 @@ static void si_set_shader_buffer(struct si_context *sctx, struct si_buffer_resou
pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
buffers->offsets[slot] = sbuffer->buffer_offset;
radeon_add_to_gfx_buffer_list_check_mem(
sctx, buf, writable ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ, priority, true);
sctx, buf, (writable ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ) | priority, true);
if (writable)
buffers->writable_mask |= 1llu << slot;
else
@@ -1517,8 +1517,8 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource
}
pipe_resource_reference(&buffers->buffers[slot], buffer);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READWRITE,
buffers->priority);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer),
RADEON_USAGE_READWRITE | buffers->priority);
buffers->enabled_mask |= 1llu << slot;
} else {
/* Clear the descriptor. */
@@ -1624,7 +1624,7 @@ static bool si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_
radeon_add_to_gfx_buffer_list_check_mem(
sctx, si_resource(buffer),
buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
(buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ) |
priority, true);
noop = false;
}
@@ -1682,7 +1682,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
sctx->descriptors_dirty |= 1u << SI_DESCS_INTERNAL;
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE,
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE |
RADEON_PRIO_SHADER_RW_BUFFER, true);
/* Update the streamout state. */
@@ -1739,7 +1739,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
descs->list + desc_slot * 16 + 4);
sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ |
RADEON_PRIO_SAMPLER_BUFFER, true);
}
}
@@ -1770,7 +1770,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
RADEON_USAGE_READWRITE,
RADEON_USAGE_READWRITE |
RADEON_PRIO_SAMPLER_BUFFER, true);
if (shader == PIPE_SHADER_COMPUTE)
@@ -1796,7 +1796,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
(*tex_handle)->desc_dirty = true;
sctx->bindless_descriptors_dirty = true;
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ,
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_READ |
RADEON_PRIO_SAMPLER_BUFFER, true);
}
}
@@ -1822,7 +1822,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
sctx->bindless_descriptors_dirty = true;
radeon_add_to_gfx_buffer_list_check_mem(
sctx, si_resource(buffer), RADEON_USAGE_READWRITE, RADEON_PRIO_SAMPLER_BUFFER, true);
sctx, si_resource(buffer), RADEON_USAGE_READWRITE | RADEON_PRIO_SAMPLER_BUFFER, true);
}
}
}
src/gallium/drivers/radeonsi/si_fence.c
+6 -6
View File
@@ -97,8 +97,8 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne
radeon_emit(scratch->gpu_address);
radeon_emit(scratch->gpu_address >> 32);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch,
RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
}
radeon_emit(PKT3(PKT3_RELEASE_MEM, ctx->chip_class >= GFX9 ? 6 : 5, 0));
@@ -126,8 +126,8 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne
radeon_emit(0); /* immediate data */
radeon_emit(0); /* unused */
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch,
RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
}
radeon_emit(PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
@@ -141,7 +141,7 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne
radeon_end();
if (buf) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
}
}
@@ -254,7 +254,7 @@ static void si_fine_fence_set(struct si_context *ctx, struct si_fine_fence *fine
} else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
uint64_t fence_va = fine->buf->gpu_address + fine->offset;
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
si_cp_release_mem(ctx, &ctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM,
EOP_INT_SEL_NONE, EOP_DATA_SEL_VALUE_32BIT, NULL, fence_va, 0x80000000,
PIPE_QUERY_GPU_FINISHED);
src/gallium/drivers/radeonsi/si_gfx_cs.c
+6 -7
View File
@@ -196,15 +196,15 @@ static void si_begin_gfx_cs_debug(struct si_context *ctx)
si_trace_emit(ctx);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
RADEON_USAGE_READWRITE, RADEON_PRIO_FENCE_TRACE);
RADEON_USAGE_READWRITE | RADEON_PRIO_FENCE_TRACE);
}
static void si_add_gds_to_buffer_list(struct si_context *sctx)
{
if (sctx->gds) {
sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds, RADEON_USAGE_READWRITE, 0, 0);
sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds, RADEON_USAGE_READWRITE, 0);
if (sctx->gds_oa) {
sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds_oa, RADEON_USAGE_READWRITE, 0, 0);
sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds_oa, RADEON_USAGE_READWRITE, 0);
}
}
}
@@ -387,12 +387,11 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
if (ctx->border_color_buffer) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer,
RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
RADEON_USAGE_READ | RADEON_PRIO_BORDER_COLORS);
}
if (ctx->shadowed_regs) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->shadowed_regs,
RADEON_USAGE_READWRITE,
RADEON_PRIO_DESCRIPTORS);
RADEON_USAGE_READWRITE | RADEON_PRIO_DESCRIPTORS);
}
si_add_all_descriptors_to_bo_list(ctx);
@@ -410,7 +409,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
if (ctx->tess_rings) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs,
unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings),
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS);
}
/* set all valid group as dirty so they get reemited on
src/gallium/drivers/radeonsi/si_pipe.c
+1 -1
View File
@@ -1011,7 +1011,7 @@ static void si_test_gds_memory_management(struct si_context *sctx, unsigned allo
SI_OP_CPDMA_SKIP_CHECK_CS_SPACE, 0,
0);
ws->cs_add_buffer(&cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain, 0);
ws->cs_add_buffer(&cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain);
ws->cs_flush(&cs[i], PIPE_FLUSH_ASYNC, NULL);
}
}
src/gallium/drivers/radeonsi/si_pipe.h
+6 -8
View File
@@ -1315,7 +1315,7 @@ bool si_nir_is_output_const_if_tex_is_const(nir_shader *shader, float *in, float
/* si_buffer.c */
bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
enum radeon_bo_usage usage);
unsigned usage);
void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
unsigned usage);
void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
@@ -1940,12 +1940,11 @@ static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_dra
* rebuilt.
*/
static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
struct si_resource *bo, enum radeon_bo_usage usage,
unsigned priority)
struct si_resource *bo, unsigned usage)
{
assert(usage);
sctx->ws->cs_add_buffer(cs, bo->buf, (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
bo->domains, priority);
sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED,
bo->domains);
}
/**
@@ -1965,15 +1964,14 @@ static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct rad
*/
static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
struct si_resource *bo,
enum radeon_bo_usage usage,
unsigned priority,
unsigned usage,
bool check_mem)
{
if (check_mem &&
!radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usage_kb))
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage, priority);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage);
}
static inline unsigned si_get_wave_size(struct si_screen *sscreen,
src/gallium/drivers/radeonsi/si_pm4.c
+1 -1
View File
@@ -119,7 +119,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
if (state->is_shader) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo,
RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
}
radeon_begin(cs);
src/gallium/drivers/radeonsi/si_query.c
+5 -5
View File
@@ -808,8 +808,8 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_h
default:
assert(0);
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf,
RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
}
static void si_query_hw_emit_start(struct si_context *sctx, struct si_query_hw *query)
@@ -889,8 +889,8 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw
default:
assert(0);
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf,
RADEON_USAGE_WRITE | RADEON_PRIO_QUERY);
if (fence_va) {
si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
@@ -947,7 +947,7 @@ static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf,
}
radeon_end();
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ, RADEON_PRIO_QUERY);
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ | RADEON_PRIO_QUERY);
}
static void si_emit_query_predication(struct si_context *ctx)
src/gallium/drivers/radeonsi/si_sdma_copy_image.c
+2 -2
View File
@@ -464,9 +464,9 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct
return false;
}
radeon_add_to_buffer_list(sctx, sctx->sdma_cs, &src->buffer, RADEON_USAGE_READ,
radeon_add_to_buffer_list(sctx, sctx->sdma_cs, &src->buffer, RADEON_USAGE_READ |
RADEON_PRIO_SAMPLER_TEXTURE);
radeon_add_to_buffer_list(sctx, sctx->sdma_cs, &dst->buffer, RADEON_USAGE_WRITE,
radeon_add_to_buffer_list(sctx, sctx->sdma_cs, &dst->buffer, RADEON_USAGE_WRITE |
RADEON_PRIO_SAMPLER_TEXTURE);
unsigned flags = RADEON_FLUSH_START_NEXT_GFX_IB_NOW;
src/gallium/drivers/radeonsi/si_sqtt.c
+2 -4
View File
@@ -386,8 +386,7 @@ si_thread_trace_start(struct si_context *sctx, int family, struct radeon_cmdbuf
ws->cs_add_buffer(cs,
sctx->thread_trace->bo,
RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM,
0);
RADEON_DOMAIN_VRAM);
si_cp_dma_wait_for_idle(sctx, cs);
@@ -429,8 +428,7 @@ si_thread_trace_stop(struct si_context *sctx, int family, struct radeon_cmdbuf *
ws->cs_add_buffer(cs,
sctx->thread_trace->bo,
RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM,
0);
RADEON_DOMAIN_VRAM);
si_cp_dma_wait_for_idle(sctx, cs);
src/gallium/drivers/radeonsi/si_state.c
+6 -6
View File
@@ -3063,12 +3063,12 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
tex = (struct si_texture *)cb->base.texture;
radeon_add_to_buffer_list(
sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC,
tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER);
sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
(tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC,
RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
RADEON_PRIO_SEPARATE_META);
}
@@ -3273,9 +3273,9 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
unsigned db_stencil_info = zb->db_stencil_info;
unsigned db_htile_surface = zb->db_htile_surface;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE,
zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
: RADEON_PRIO_DEPTH_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
(zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
: RADEON_PRIO_DEPTH_BUFFER));
/* Set fields dependent on tc_compatile_htile. */
if (sctx->chip_class >= GFX9 &&
src/gallium/drivers/radeonsi/si_state_draw.cpp
+8 -8
View File
@@ -1385,8 +1385,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
index_va = si_resource(indexbuf)->gpu_address + index_offset;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indexbuf), RADEON_USAGE_READ,
RADEON_PRIO_INDEX_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indexbuf),
RADEON_USAGE_READ | RADEON_PRIO_INDEX_BUFFER);
} else {
/* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
* so the state must be re-emitted before the next indexed draw.
@@ -1412,7 +1412,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
radeon_emit(indirect_va >> 32);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indirect->buffer),
RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
@@ -1440,8 +1440,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
if (indirect->indirect_draw_count) {
struct si_resource *params_buf = si_resource(indirect->indirect_draw_count);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, params_buf, RADEON_USAGE_READ,
RADEON_PRIO_DRAW_INDIRECT);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, params_buf,
RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
}
@@ -1795,7 +1795,7 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx,
sctx->vb_descriptors_gpu_list = ptr;
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->vb_descriptors_buffer,
RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
RADEON_USAGE_READ | RADEON_PRIO_DESCRIPTORS);
/* GFX6 doesn't support the L2 prefetch. */
if (GFX_VERSION >= GFX7)
si_cp_dma_prefetch(sctx, &sctx->vb_descriptors_buffer->b.b, sctx->vb_descriptors_offset,
@@ -1831,7 +1831,7 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx,
if (vstate->b.input.vbuffer.buffer.resource != vstate->b.input.indexbuf) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs,
si_resource(vstate->b.input.vbuffer.buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
}
/* The next draw_vbo should recompute and rebind vertex buffer descriptors. */
@@ -1853,7 +1853,7 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx,
if (first_vb_use_mask & (1 << i)) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(vb->buffer.resource),
RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
}
}
src/gallium/drivers/radeonsi/si_state_shaders.cpp
+3 -3
View File
@@ -3956,7 +3956,7 @@ void si_init_tess_factor_ring(struct si_context *sctx)
assert(sctx->chip_class >= GFX7);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(sctx->tess_rings),
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS);
si_emit_vgt_flush(cs);
/* Set tessellation registers. */
@@ -4074,8 +4074,8 @@ static void si_emit_scratch_state(struct si_context *sctx)
radeon_end();
if (sctx->scratch_buffer) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->scratch_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->scratch_buffer,
RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
}
}
src/gallium/drivers/radeonsi/si_state_streamout.c
+6 -6
View File
@@ -234,8 +234,8 @@ static void gfx10_emit_streamout_begin(struct si_context *sctx)
uint64_t va = 0;
if (append) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_READ,
RADEON_PRIO_SO_FILLED_SIZE);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
}
@@ -339,8 +339,8 @@ static void si_emit_streamout_begin(struct si_context *sctx)
radeon_emit(va); /* src address lo */
radeon_emit(va >> 32); /* src address hi */
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_READ,
RADEON_PRIO_SO_FILLED_SIZE);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
} else {
/* Start from the beginning. */
radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
@@ -386,8 +386,8 @@ void si_emit_streamout_end(struct si_context *sctx)
radeon_emit(0); /* unused */
radeon_emit(0); /* unused */
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_WRITE,
RADEON_PRIO_SO_FILLED_SIZE);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);
/* Zero the buffer size. The counters (primitives generated,
* primitives emitted) may be enabled even if there is not
src/gallium/drivers/radeonsi/si_state_viewport.c
+1 -1
View File
@@ -102,7 +102,7 @@ static void si_emit_cull_state(struct si_context *sctx)
/* This will end up in SGPR6 as (value << 8), shifted by the hw. */
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf,
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
radeon_begin(&sctx->gfx_cs);
radeon_set_sh_reg(R_00B220_SPI_SHADER_PGM_LO_GS,
sctx->small_prim_cull_info_address >> 8);
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+1 -1
View File
@@ -49,7 +49,7 @@ struct amdgpu_sparse_backing_chunk {
static bool amdgpu_bo_wait(struct radeon_winsys *rws,
struct pb_buffer *_buf, uint64_t timeout,
enum radeon_bo_usage usage)
unsigned usage)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+16 -20
View File
@@ -574,7 +574,7 @@ static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_winsys *ws,
memset(buffer, 0, sizeof(*buffer));
amdgpu_winsys_bo_reference(ws, &buffer->bo, bo);
buffer->u.slab.real_idx = real_idx;
buffer->slab_real_idx = real_idx;
cs->num_slab_buffers++;
hash = bo->unique_id & (BUFFER_HASHLIST_SIZE-1);
@@ -643,9 +643,8 @@ static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_winsys *ws,
static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
struct pb_buffer *buf,
enum radeon_bo_usage usage,
enum radeon_bo_domain domains,
unsigned priority)
unsigned usage,
enum radeon_bo_domain domains)
{
/* Don't use the "domains" parameter. Amdgpu doesn't support changing
* the buffer placement during command submission.
@@ -661,8 +660,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
* are outside of the winsys.
*/
if (bo == cs->last_added_bo &&
(usage & cs->last_added_bo_usage) == usage &&
priority & cs->last_added_bo_priority_usage)
(usage & cs->last_added_bo_usage) == usage)
return cs->last_added_bo_index;
if (!(bo->base.usage & RADEON_FLAG_SPARSE)) {
@@ -675,7 +673,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
buffer->usage |= usage;
usage &= ~RADEON_USAGE_SYNCHRONIZED;
index = buffer->u.slab.real_idx;
index = buffer->slab_real_idx;
} else {
index = amdgpu_lookup_or_add_real_buffer(rcs, acs, bo);
if (index < 0)
@@ -691,13 +689,11 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
buffer = &cs->sparse_buffers[index];
}
buffer->u.real.priority_usage |= priority;
buffer->usage |= usage;
cs->last_added_bo = bo;
cs->last_added_bo_index = index;
cs->last_added_bo_usage = buffer->usage;
cs->last_added_bo_priority_usage = buffer->u.real.priority_usage;
return index;
}
@@ -807,7 +803,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
ib->ptr_ib_size_inside_ib = false;
amdgpu_cs_add_buffer(cs->main.rcs, ib->big_ib_buffer,
RADEON_USAGE_READ, 0, RADEON_PRIO_IB);
RADEON_USAGE_READ | RADEON_PRIO_IB, 0);
rcs->current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
@@ -1060,8 +1056,8 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
assert(!cs->preamble_ib_bo);
cs->preamble_ib_bo = preamble_bo;
amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0,
RADEON_PRIO_IB);
amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo,
RADEON_USAGE_READ | RADEON_PRIO_IB, 0);
return true;
}
@@ -1152,7 +1148,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
rcs->gpu_address = va;
amdgpu_cs_add_buffer(cs->main.rcs, ib->big_ib_buffer,
RADEON_USAGE_READ, 0, RADEON_PRIO_IB);
RADEON_USAGE_READ | RADEON_PRIO_IB, 0);
return true;
}
@@ -1167,7 +1163,7 @@ static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf *rcs,
for (i = 0; i < cs->num_real_buffers; i++) {
list[i].bo_size = cs->real_buffers[i].bo->base.size;
list[i].vm_address = cs->real_buffers[i].bo->va;
list[i].priority_usage = cs->real_buffers[i].u.real.priority_usage;
list[i].priority_usage = cs->real_buffers[i].usage;
}
}
return cs->num_real_buffers;
@@ -1368,7 +1364,7 @@ static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_winsys *ws,
return false;
}
cs->real_buffers[idx].u.real.priority_usage = buffer->u.real.priority_usage;
cs->real_buffers[idx].usage = buffer->usage;
}
simple_mtx_unlock(&bo->lock);
@@ -1429,10 +1425,10 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
unsigned num_handles = 0;
for (i = 0; i < cs->num_real_buffers; ++i) {
struct amdgpu_cs_buffer *buffer = &cs->real_buffers[i];
assert(buffer->u.real.priority_usage != 0);
list[num_handles].bo_handle = buffer->bo->u.real.kms_handle;
list[num_handles].bo_priority = (util_last_bit(buffer->u.real.priority_usage) - 1) / 2;
list[num_handles].bo_priority =
(util_last_bit(buffer->usage & RADEON_ALL_PRIORITIES) - 1) / 2;
++num_handles;
}
@@ -1769,8 +1765,8 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
amdgpu_get_new_ib(ws, rcs, &cs->main, cs);
if (cs->preamble_ib_bo) {
amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0,
RADEON_PRIO_IB);
amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo,
RADEON_USAGE_READ | RADEON_PRIO_IB, 0);
}
rcs->used_gart_kb = 0;
@@ -1805,7 +1801,7 @@ static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf *rcs,
struct pb_buffer *_buf,
enum radeon_bo_usage usage)
unsigned usage)
{
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)_buf;
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+3 -11
View File
@@ -50,15 +50,8 @@ struct amdgpu_ctx {
struct amdgpu_cs_buffer {
struct amdgpu_winsys_bo *bo;
union {
struct {
uint32_t priority_usage;
} real;
struct {
uint32_t real_idx; /* index of underlying real BO */
} slab;
} u;
enum radeon_bo_usage usage;
unsigned slab_real_idx; /* index of underlying real BO, used by slab buffers only */
unsigned usage;
};
enum ib_type {
@@ -115,7 +108,6 @@ struct amdgpu_cs_context {
struct amdgpu_winsys_bo *last_added_bo;
unsigned last_added_bo_index;
unsigned last_added_bo_usage;
uint32_t last_added_bo_priority_usage;
struct amdgpu_fence_list fence_dependencies;
struct amdgpu_fence_list syncobj_dependencies;
@@ -243,7 +235,7 @@ amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
static inline bool
amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
struct amdgpu_winsys_bo *bo,
enum radeon_bo_usage usage)
unsigned usage)
{
int index;
struct amdgpu_cs_buffer *buffer;
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+1 -1
View File
@@ -131,7 +131,7 @@ static void radeon_bo_wait_idle(struct radeon_bo *bo)
static bool radeon_bo_wait(struct radeon_winsys *rws,
struct pb_buffer *_buf, uint64_t timeout,
enum radeon_bo_usage usage)
unsigned usage)
{
struct radeon_bo *bo = radeon_bo(_buf);
int64_t abs_timeout;
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+5 -6
View File
@@ -360,9 +360,8 @@ static int radeon_lookup_or_add_slab_buffer(struct radeon_drm_cs *cs,
static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs,
struct pb_buffer *buf,
enum radeon_bo_usage usage,
enum radeon_bo_domain domains,
unsigned priority)
unsigned usage,
enum radeon_bo_domain domains)
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_bo *bo = (struct radeon_bo*)buf;
@@ -396,6 +395,7 @@ static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs,
reloc->write_domain |= wd;
/* The priority must be in [0, 15]. It's used by the kernel memory management. */
unsigned priority = usage & RADEON_ALL_PRIORITIES;
unsigned bo_priority = util_last_bit(priority) / 2;
reloc->flags = MAX2(reloc->flags, bo_priority);
cs->csc->relocs_bo[index].u.real.priority_usage |= priority;
@@ -751,7 +751,7 @@ static void radeon_drm_cs_destroy(struct radeon_cmdbuf *rcs)
static bool radeon_bo_is_referenced(struct radeon_cmdbuf *rcs,
struct pb_buffer *_buf,
enum radeon_bo_usage usage)
unsigned usage)
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_bo *bo = (struct radeon_bo*)_buf;
@@ -792,8 +792,7 @@ static struct pipe_fence_handle *radeon_cs_create_fence(struct radeon_cmdbuf *rc
/* Add the fence as a dummy relocation. */
cs->ws->base.cs_add_buffer(rcs, fence,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT,
RADEON_PRIO_FENCE_TRACE);
RADEON_USAGE_READWRITE | RADEON_PRIO_FENCE_TRACE, RADEON_DOMAIN_GTT);
return (struct pipe_fence_handle*)fence;
}