AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

iris: add required invalidate/flush for Wa_14014427904

Browse Source 
This WA impacts skus with multiple CCS, e.g. ATS-M. According to
description, we need to add a pipe control before following NP state
commands:

   STATE_BASE_ADDRESS
   3DSTATE_BTD
   CHROMA_KEY
   STATE_SIP
   STATE_COMPUTE_MODE

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20784>
This commit is contained in:
Tapani Pälli
2023-01-18 14:11:53 +02:00
committed by Marge Bot
parent 60b0d2c2cb
commit 613eb64011
1 changed files with 15 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/iris/iris_state.c
+15
View File
@@ -384,6 +384,20 @@ emit_state(struct iris_batch *batch,
static void
flush_before_state_base_change(struct iris_batch *batch)
{
/* Wa_14014427904 - We need additional invalidate/flush when
* emitting NP state commands with ATS-M in compute mode.
*/
bool atsm_compute = intel_device_info_is_atsm(batch->screen->devinfo) &&
batch->name == IRIS_BATCH_COMPUTE;
uint32_t np_state_wa_bits =
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_FLUSH_HDC;
/* Flush before emitting STATE_BASE_ADDRESS.
*
* This isn't documented anywhere in the PRM. However, it seems to be
@@ -407,6 +421,7 @@ flush_before_state_base_change(struct iris_batch *batch)
*/
iris_emit_end_of_pipe_sync(batch,
"change STATE_BASE_ADDRESS (flushes)",
atsm_compute ? np_state_wa_bits : 0 |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DATA_CACHE_FLUSH);