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broadcom/vc5: Drop alignment bits from Z/S rendering mode config address.

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Improves CLIF dumping output.
This commit is contained in:
Eric Anholt
2017-10-24 19:13:17 -07:00
parent d0f7053369
commit 607031f411
1 changed files with 1 additions and 1 deletions
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src/broadcom/cle/v3d_packet_v33.xml
+1 -1
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@@ -528,7 +528,7 @@
</packet>
<packet code="121" name="Tile Rendering Mode Configuration (Z/Stencil config)" cl="R">
<field name="Address" size="32" start="32" type="address"/>
<field name="Address" size="26" start="38" type="address"/>
<field name="Padded height of output image in UIF blocks" size="13" start="25" type="uint"/>