iris: Enable HIZ_CCS in depth buffer instructions
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@@ -478,7 +478,8 @@ iris_resource_configure_aux(struct iris_screen *screen,
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} else if (has_mcs) {
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res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS;
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} else if (has_hiz) {
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res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
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res->aux.possible_usages |=
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1 << (has_ccs ? ISL_AUX_USAGE_HIZ_CCS : ISL_AUX_USAGE_HIZ);
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} else if (has_ccs) {
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if (want_ccs_e_for_format(devinfo, res->surf.format))
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res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;
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@@ -497,6 +498,9 @@ iris_resource_configure_aux(struct iris_screen *screen,
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if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
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res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
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/* We don't yet support sampling with HIZ_CCS. */
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res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
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enum isl_aux_state initial_state;
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*aux_size_B = 0;
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*alloc_flags = 0;
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@@ -572,7 +576,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
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size += iris_get_aux_clear_color_state_size(screen);
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*aux_size_B = size;
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if (res->aux.usage == ISL_AUX_USAGE_HIZ) {
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if (isl_aux_usage_has_hiz(res->aux.usage)) {
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for (unsigned level = 0; level < res->surf.levels; ++level) {
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uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
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uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
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@@ -2985,7 +2985,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
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view.format = zres->surf.format;
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if (iris_resource_level_has_hiz(zres, view.base_level)) {
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info.hiz_usage = ISL_AUX_USAGE_HIZ;
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info.hiz_usage = zres->aux.usage;
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info.hiz_surf = &zres->aux.surf;
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info.hiz_address = zres->aux.bo->gtt_offset + zres->aux.offset;
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}
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