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r600/llvm: remove dead code for LLVM 3.3

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LLVM 3.3 has been unsupported for quite a while.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák
2015-09-06 16:19:33 +02:00
parent 5c6c5b5246
commit 5fbfd8dd23
1 changed files with 0 additions and 106 deletions
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src/gallium/drivers/r600/r600_llvm.c
-106
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@@ -77,22 +77,11 @@ static void llvm_load_system_value(
default: assert(!"unknown system value");
}
#if HAVE_LLVM >= 0x0304
ctx->system_values[index] = LLVMBuildExtractElement(ctx->gallivm.builder,
LLVMGetParam(ctx->main_fn, 0), lp_build_const_int32(&(ctx->gallivm), chan),
"");
#else
LLVMValueRef reg = lp_build_const_int32(
ctx->soa.bld_base.base.gallivm, chan);
ctx->system_values[index] = lp_build_intrinsic(
ctx->soa.bld_base.base.gallivm->builder,
"llvm.R600.load.input",
ctx->soa.bld_base.base.elem_type, &reg, 1,
LLVMReadNoneAttribute);
#endif
}
#if HAVE_LLVM >= 0x0304
static LLVMValueRef
llvm_load_input_vector(
struct radeon_llvm_context * ctx, unsigned location, unsigned ijregs,
@@ -131,34 +120,7 @@ llvm_load_input_vector(
VecType, Args, ArgCount, LLVMReadNoneAttribute);
}
}
#else
static LLVMValueRef
llvm_load_input_helper(
struct radeon_llvm_context * ctx,
unsigned idx, int interp, int ij_index)
{
const struct lp_build_context * bb = &ctx->soa.bld_base.base;
LLVMValueRef arg[2];
int arg_count;
const char * intrinsic;
arg[0] = lp_build_const_int32(bb->gallivm, idx);
if (interp) {
intrinsic = "llvm.R600.interp.input";
arg[1] = lp_build_const_int32(bb->gallivm, ij_index);
arg_count = 2;
} else {
intrinsic = "llvm.R600.load.input";
arg_count = 1;
}
return lp_build_intrinsic(bb->gallivm->builder, intrinsic,
bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
}
#endif
#if HAVE_LLVM >= 0x0304
static LLVMValueRef
llvm_face_select_helper(
struct radeon_llvm_context * ctx,
@@ -171,21 +133,6 @@ llvm_face_select_helper(
return LLVMBuildSelect(bb->gallivm->builder, is_front,
front_color, back_color, "");
}
#else
static LLVMValueRef
llvm_face_select_helper(
struct radeon_llvm_context * ctx,
unsigned face_loc, LLVMValueRef front_color, LLVMValueRef back_color)
{
const struct lp_build_context * bb = &ctx->soa.bld_base.base;
LLVMValueRef face = llvm_load_input_helper(ctx, face_loc, 0, 0);
LLVMValueRef is_front = LLVMBuildFCmp(
bb->gallivm->builder, LLVMRealUGT, face,
lp_build_const_float(bb->gallivm, 0.0f), "");
return LLVMBuildSelect(bb->gallivm->builder, is_front,
front_color, back_color, "");
}
#endif
static void llvm_load_input(
struct radeon_llvm_context * ctx,
@@ -194,18 +141,11 @@ static void llvm_load_input(
{
const struct r600_shader_io * input = &ctx->r600_inputs[input_index];
unsigned chan;
#if HAVE_LLVM < 0x0304
unsigned interp = 0;
int ij_index;
#endif
int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR);
LLVMValueRef v;
#if HAVE_LLVM >= 0x0304
boolean require_interp_intrinsic = ctx->chip_class >= EVERGREEN &&
ctx->type == TGSI_PROCESSOR_FRAGMENT;
#endif
#if HAVE_LLVM >= 0x0304
if (require_interp_intrinsic && input->spi_sid) {
v = llvm_load_input_vector(ctx, input->lds_pos, input->ij_index,
(input->interpolate > 0));
@@ -241,49 +181,7 @@ static void llvm_load_input(
lp_build_const_float(&(ctx->gallivm), 1.0f),
ctx->inputs[soa_index], "");
}
}
#else
if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT &&
input->spi_sid) {
interp = 1;
ij_index = (input->interpolate > 0) ? input->ij_index : -1;
}
for (chan = 0; chan < 4; chan++) {
unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
int loc;
if (interp) {
loc = 4 * input->lds_pos + chan;
} else {
if (input->name == TGSI_SEMANTIC_FACE)
loc = 4 * ctx->face_gpr;
else
loc = 4 * input->gpr + chan;
}
v = llvm_load_input_helper(ctx, loc, interp, ij_index);
if (two_side) {
struct r600_shader_io * back_input =
&ctx->r600_inputs[input->back_color_input];
int back_loc = interp ? back_input->lds_pos : back_input->gpr;
LLVMValueRef v2;
back_loc = 4 * back_loc + chan;
v2 = llvm_load_input_helper(ctx, back_loc, interp, ij_index);
v = llvm_face_select_helper(ctx, 4 * ctx->face_gpr, v, v2);
} else if (input->name == TGSI_SEMANTIC_POSITION &&
ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) {
/* RCP for fragcoord.w */
v = LLVMBuildFDiv(ctx->gallivm.builder,
lp_build_const_float(&(ctx->gallivm), 1.0f),
v, "");
}
ctx->inputs[soa_index] = v;
}
#endif
}
static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
@@ -887,7 +785,6 @@ LLVMModuleRef r600_tgsi_llvm(
struct tgsi_shader_info shader_info;
struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
radeon_llvm_context_init(ctx);
#if HAVE_LLVM >= 0x0304
LLVMTypeRef Arguments[32];
unsigned ArgumentsCount = 0;
for (unsigned i = 0; i < ctx->inputs_count; i++)
@@ -897,9 +794,6 @@ LLVMModuleRef r600_tgsi_llvm(
LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
LLVMAddAttribute(P, LLVMInRegAttribute);
}
#else
radeon_llvm_create_func(ctx, NULL, 0);
#endif
tgsi_scan_shader(tokens, &shader_info);
bld_base->info = &shader_info;