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intel/fs/xe2+: Teach SWSB pass about the behavior of double precision instructions.

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Xe2 hardware has a "long" EU pipeline specifically for FP64
instructions, so these are handled as in-order instructions which
require RegDist synchronization.  64-bit integer instructions are now
handled by the normal integer pipeline, so the existing special-casing
inherited from ATS needs to be disabled.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25514>
This commit is contained in:
Francisco Jerez
2022-02-19 01:41:55 -08:00
parent 9e446c9282
commit 5fb6760f11
1 changed files with 7 additions and 2 deletions
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9
src/intel/compiler/brw_fs_scoreboard.cpp
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@@ -135,8 +135,13 @@ namespace {
return TGL_PIPE_INT;
else if (inst->opcode == FS_OPCODE_PACK_HALF_2x16_SPLIT)
return TGL_PIPE_FLOAT;
else if (type_sz(inst->dst.type) >= 8 || type_sz(t) >= 8 ||
is_dword_multiply) {
else if (devinfo->ver >= 20 && type_sz(inst->dst.type) >= 8 &&
brw_reg_type_is_floating_point(inst->dst.type)) {
assert(devinfo->has_64bit_float);
return TGL_PIPE_LONG;
} else if (devinfo->ver < 20 &&
(type_sz(inst->dst.type) >= 8 || type_sz(t) >= 8 ||
is_dword_multiply)) {
assert(devinfo->has_64bit_float || devinfo->has_64bit_int ||
devinfo->has_integer_dword_mul);
return TGL_PIPE_LONG;