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i965/nir: Pass a is_scalar boolean to brw_create_nir()

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The upcoming introduction of NIR->vec4 pass will require that some NIR
lowering passes are enabled/disabled depending on the type of shader
(scalar vs. vector).

With this patch we pass a 'is_scalar' variable to the process of
constructing the NIR, to let an external context decide how the shader
should be handled.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
This commit is contained in:
Eduardo Lima Mitev
2015-07-22 09:35:28 +02:00
committed by Jason Ekstrand
parent 59006d3ad3
commit 5e839727ed
5 changed files with 12 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_nir.c
+2 -1
View File
@@ -61,7 +61,8 @@ nir_shader *
brw_create_nir(struct brw_context *brw,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
gl_shader_stage stage)
gl_shader_stage stage,
bool is_scalar)
{
struct gl_context *ctx = &brw->ctx;
const nir_shader_compiler_options *options =
src/mesa/drivers/dri/i965/brw_nir.h
+2 -1
View File
@@ -77,7 +77,8 @@ void brw_nir_analyze_boolean_resolves(nir_shader *nir);
nir_shader *brw_create_nir(struct brw_context *brw,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
gl_shader_stage stage);
gl_shader_stage stage,
bool is_scalar);
#ifdef __cplusplus
}
src/mesa/drivers/dri/i965/brw_program.c
+3 -2
View File
@@ -143,7 +143,7 @@ brwProgramStringNotify(struct gl_context *ctx,
brw_add_texrect_params(prog);
if (ctx->Const.ShaderCompilerOptions[MESA_SHADER_FRAGMENT].NirOptions) {
prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT);
prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT, true);
}
brw_fs_precompile(ctx, NULL, prog);
@@ -169,7 +169,8 @@ brwProgramStringNotify(struct gl_context *ctx,
brw_add_texrect_params(prog);
if (ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].NirOptions) {
prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_VERTEX);
prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_VERTEX,
brw->intelScreen->compiler->scalar_vs);
}
brw_vs_precompile(ctx, NULL, prog);
src/mesa/drivers/dri/i965/brw_shader.cpp
+4 -2
View File
@@ -398,8 +398,10 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
brw_add_texrect_params(prog);
if (options->NirOptions)
prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
if (options->NirOptions) {
prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
is_scalar_shader_stage(brw, stage));
}
_mesa_reference_program(ctx, &prog, NULL);
}
src/mesa/drivers/dri/i965/brw_vec4.cpp
+1 -1
View File
@@ -1919,7 +1919,7 @@ brw_vs_emit(struct brw_context *brw,
*/
assert(vp->Base.Id == 0 && prog == NULL);
vp->Base.nir =
brw_create_nir(brw, NULL, &vp->Base, MESA_SHADER_VERTEX);
brw_create_nir(brw, NULL, &vp->Base, MESA_SHADER_VERTEX, true);
}
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;