i965: Move is_math/is_tex/is_control_flow() to backend_instruction.

These are entirely based on the opcode, which is available in
backend_instruction.  It makes sense to only implement them in one
place.

This changes the VS implementation of is_tex() slightly, which now
accepts FS_OPCODE_TXB and SHADER_OPCODE_LOD.  However, since those
aren't generated in the VS anyway, it should be fine.

This also makes is_control_flow() available in the VS.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

src/mesa/drivers/dri/i965/brw_fs.cpp

@@ -339,51 +339,6 @@ fs_inst::overwrites_reg(const fs_reg &reg)
            reg.reg_offset < dst.reg_offset + regs_written);
 }
 
-bool
-fs_inst::is_tex()
-{
-   return (opcode == SHADER_OPCODE_TEX ||
-           opcode == FS_OPCODE_TXB ||
-           opcode == SHADER_OPCODE_TXD ||
-           opcode == SHADER_OPCODE_TXF ||
-           opcode == SHADER_OPCODE_TXF_MS ||
-           opcode == SHADER_OPCODE_TXL ||
-           opcode == SHADER_OPCODE_TXS ||
-           opcode == SHADER_OPCODE_LOD);
-}
-
-bool
-fs_inst::is_math()
-{
-   return (opcode == SHADER_OPCODE_RCP ||
-           opcode == SHADER_OPCODE_RSQ ||
-           opcode == SHADER_OPCODE_SQRT ||
-           opcode == SHADER_OPCODE_EXP2 ||
-           opcode == SHADER_OPCODE_LOG2 ||
-           opcode == SHADER_OPCODE_SIN ||
-           opcode == SHADER_OPCODE_COS ||
-           opcode == SHADER_OPCODE_INT_QUOTIENT ||
-           opcode == SHADER_OPCODE_INT_REMAINDER ||
-           opcode == SHADER_OPCODE_POW);
-}
-
-bool
-fs_inst::is_control_flow()
-{
-   switch (opcode) {
-   case BRW_OPCODE_DO:
-   case BRW_OPCODE_WHILE:
-   case BRW_OPCODE_IF:
-   case BRW_OPCODE_ELSE:
-   case BRW_OPCODE_ENDIF:
-   case BRW_OPCODE_BREAK:
-   case BRW_OPCODE_CONTINUE:
-      return true;
-   default:
-      return false;
-   }
-}
-
 bool
 fs_inst::is_send_from_grf()
 {

src/mesa/drivers/dri/i965/brw_fs.h

@@ -175,9 +175,6 @@ public:
 
    bool equals(fs_inst *inst);
    bool overwrites_reg(const fs_reg &reg);
-   bool is_tex();
-   bool is_math();
-   bool is_control_flow();
    bool is_send_from_grf();
    bool is_partial_write();
 

src/mesa/drivers/dri/i965/brw_shader.cpp

@@ -508,3 +508,48 @@ brw_instruction_name(enum opcode op)
       return fallback;
    }
 }
+
+bool
+backend_instruction::is_tex()
+{
+   return (opcode == SHADER_OPCODE_TEX ||
+           opcode == FS_OPCODE_TXB ||
+           opcode == SHADER_OPCODE_TXD ||
+           opcode == SHADER_OPCODE_TXF ||
+           opcode == SHADER_OPCODE_TXF_MS ||
+           opcode == SHADER_OPCODE_TXL ||
+           opcode == SHADER_OPCODE_TXS ||
+           opcode == SHADER_OPCODE_LOD);
+}
+
+bool
+backend_instruction::is_math()
+{
+   return (opcode == SHADER_OPCODE_RCP ||
+           opcode == SHADER_OPCODE_RSQ ||
+           opcode == SHADER_OPCODE_SQRT ||
+           opcode == SHADER_OPCODE_EXP2 ||
+           opcode == SHADER_OPCODE_LOG2 ||
+           opcode == SHADER_OPCODE_SIN ||
+           opcode == SHADER_OPCODE_COS ||
+           opcode == SHADER_OPCODE_INT_QUOTIENT ||
+           opcode == SHADER_OPCODE_INT_REMAINDER ||
+           opcode == SHADER_OPCODE_POW);
+}
+
+bool
+backend_instruction::is_control_flow()
+{
+   switch (opcode) {
+   case BRW_OPCODE_DO:
+   case BRW_OPCODE_WHILE:
+   case BRW_OPCODE_IF:
+   case BRW_OPCODE_ELSE:
+   case BRW_OPCODE_ENDIF:
+   case BRW_OPCODE_BREAK:
+   case BRW_OPCODE_CONTINUE:
+      return true;
+   default:
+      return false;
+   }
+}

src/mesa/drivers/dri/i965/brw_shader.h

@@ -29,6 +29,10 @@
 
 class backend_instruction : public exec_node {
 public:
+   bool is_tex();
+   bool is_math();
+   bool is_control_flow();
+
    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 
    uint32_t predicate;

src/mesa/drivers/dri/i965/brw_vec4.cpp

@@ -141,17 +141,6 @@ src_reg::src_reg(dst_reg reg)
                                 swizzles[2], swizzles[3]);
 }
 
-bool
-vec4_instruction::is_tex()
-{
-   return (opcode == SHADER_OPCODE_TEX ||
-	   opcode == SHADER_OPCODE_TXD ||
-	   opcode == SHADER_OPCODE_TXF ||
-	   opcode == SHADER_OPCODE_TXF_MS ||
-	   opcode == SHADER_OPCODE_TXL ||
-	   opcode == SHADER_OPCODE_TXS);
-}
-
 void
 dst_reg::init()
 {
@@ -212,21 +201,6 @@ dst_reg::dst_reg(src_reg reg)
    this->fixed_hw_reg = reg.fixed_hw_reg;
 }
 
-bool
-vec4_instruction::is_math()
-{
-   return (opcode == SHADER_OPCODE_RCP ||
-	   opcode == SHADER_OPCODE_RSQ ||
-	   opcode == SHADER_OPCODE_SQRT ||
-	   opcode == SHADER_OPCODE_EXP2 ||
-	   opcode == SHADER_OPCODE_LOG2 ||
-	   opcode == SHADER_OPCODE_SIN ||
-	   opcode == SHADER_OPCODE_COS ||
-	   opcode == SHADER_OPCODE_INT_QUOTIENT ||
-	   opcode == SHADER_OPCODE_INT_REMAINDER ||
-	   opcode == SHADER_OPCODE_POW);
-}
-
 bool
 vec4_instruction::is_send_from_grf()
 {

src/mesa/drivers/dri/i965/brw_vec4.h

@@ -193,8 +193,6 @@ public:
    const void *ir;
    const char *annotation;
 
-   bool is_tex();
-   bool is_math();
    bool is_send_from_grf();
    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
    void reswizzle_dst(int dst_writemask, int swizzle);