freedreno/a3xx: fix MAX_INPUTS shader cap
Hardware only supports 16. Which fd3_shader_variant properly reflected, but the pipe cap did not, leading to array overflow (and shaders that could not possibly work). Also a bunch of asserts to make problems like this easier to see. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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@@ -2138,6 +2138,8 @@ decl_in(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
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DBG("decl in -> r%d", i);
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compile_assert(ctx, n < ARRAY_SIZE(so->inputs));
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so->inputs[n].semantic = decl_semantic(&decl->Semantic);
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so->inputs[n].compmask = (1 << ncomp) - 1;
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so->inputs[n].regid = r;
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@@ -2227,6 +2229,8 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
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ncomp = 4;
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compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
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so->outputs[n].semantic = decl_semantic(&decl->Semantic);
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so->outputs[n].regid = regid(i, comp);
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@@ -2350,6 +2354,7 @@ compile_instructions(struct fd3_compile_context *ctx)
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struct tgsi_full_immediate *imm =
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&ctx->parser.FullToken.FullImmediate;
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unsigned n = ctx->so->immediates_count++;
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compile_assert(ctx, n < ARRAY_SIZE(ctx->so->immediates));
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memcpy(ctx->so->immediates[n].val, imm->u, 16);
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break;
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}
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@@ -1324,6 +1324,8 @@ decl_in(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
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DBG("decl in -> r%d", i + base); // XXX
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compile_assert(ctx, n < ARRAY_SIZE(so->inputs));
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so->inputs[n].semantic = decl_semantic(&decl->Semantic);
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so->inputs[n].compmask = (1 << ncomp) - 1;
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so->inputs[n].ncomp = ncomp;
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@@ -1410,6 +1412,7 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
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for (i = decl->Range.First; i <= decl->Range.Last; i++) {
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unsigned n = so->outputs_count++;
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compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
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so->outputs[n].semantic = decl_semantic(&decl->Semantic);
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so->outputs[n].regid = regid(i + base, comp);
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}
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@@ -321,7 +321,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
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case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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return 8; /* XXX */
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case PIPE_SHADER_CAP_MAX_INPUTS:
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return 32;
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return 16;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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return 64; /* Max native temporaries. */
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case PIPE_SHADER_CAP_MAX_ADDRS:
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