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radv: add a new dirty bit for the binning state

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36875>
This commit is contained in:
Samuel Pitoiset
2025-08-19 15:20:02 +02:00
committed by Marge Bot
parent c4c44187f9
commit 5db8a16053
2 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+14 -12
View File
@@ -1741,16 +1741,16 @@ radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer)
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_cmd_stream *cs = cmd_buffer->cs;
unsigned pa_sc_binner_cntl_0;
if (pdev->info.gfx_level < GFX9)
return;
if (pdev->info.gfx_level >= GFX9) {
const uint32_t pa_sc_binner_cntl_0 = radv_get_binning_state(cmd_buffer);
pa_sc_binner_cntl_0 = radv_get_binning_state(cmd_buffer);
radeon_begin(cs);
radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0, RADV_TRACKED_PA_SC_BINNER_CNTL_0, pa_sc_binner_cntl_0);
radeon_end();
}
radeon_begin(cs);
radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0, RADV_TRACKED_PA_SC_BINNER_CNTL_0, pa_sc_binner_cntl_0);
radeon_end();
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_BINNING_STATE;
}
static void
@@ -9358,7 +9358,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
render->has_hiz_his = has_hiz_his;
render->vrs_att = vrs_att;
render->vrs_texel_size = vrs_texel_size;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER | RADV_CMD_DIRTY_FBFETCH_OUTPUT;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER | RADV_CMD_DIRTY_BINNING_STATE | RADV_CMD_DIRTY_FBFETCH_OUTPUT;
if (pdev->info.rbplus_allowed)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
@@ -11429,6 +11429,11 @@ radv_validate_dynamic_states(struct radv_cmd_buffer *cmd_buffer, uint64_t dynami
if (dynamic_states & (RADV_DYNAMIC_VIEWPORT | RADV_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE))
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VIEWPORT_STATE;
if (dynamic_states &
(RADV_DYNAMIC_COLOR_WRITE_MASK | RADV_DYNAMIC_RASTERIZATION_SAMPLES | RADV_DYNAMIC_LINE_RASTERIZATION_MODE |
RADV_DYNAMIC_PRIMITIVE_TOPOLOGY | RADV_DYNAMIC_POLYGON_MODE))
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_BINNING_STATE;
}
static void
@@ -11488,10 +11493,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
cmd_buffer->state.has_nggc)
radv_emit_ngg_culling_state(cmd_buffer);
if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
(cmd_buffer->state.dirty_dynamic &
(RADV_DYNAMIC_COLOR_WRITE_MASK | RADV_DYNAMIC_RASTERIZATION_SAMPLES | RADV_DYNAMIC_LINE_RASTERIZATION_MODE |
RADV_DYNAMIC_PRIMITIVE_TOPOLOGY | RADV_DYNAMIC_POLYGON_MODE)))
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_BINNING_STATE)
radv_emit_binning_state(cmd_buffer);
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
src/amd/vulkan/radv_cmd_buffer.h
+2 -1
View File
@@ -106,7 +106,8 @@ enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_TESS_STATE = 1ull << 20,
RADV_CMD_DIRTY_CB_RENDER_STATE = 1ull << 21,
RADV_CMD_DIRTY_VIEWPORT_STATE = 1ull << 22,
RADV_CMD_DIRTY_ALL = (1ull << 23) - 1,
RADV_CMD_DIRTY_BINNING_STATE = 1ull << 23,
RADV_CMD_DIRTY_ALL = (1ull << 24) - 1,
RADV_CMD_DIRTY_SHADER_QUERY = RADV_CMD_DIRTY_NGG_STATE | RADV_CMD_DIRTY_TASK_STATE,
};