r600g: Add support for PK2H/UP2H
Based off of Ilia's original patch, but with output values replicated so that it matches the TGSI semantics. Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Glenn Kennard
committed by
Marek Olšák
Marek Olšák
parent
eb2dc04127
commit
5da24242b3
@@ -335,6 +335,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
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return family >= CHIP_CEDAR ? 1 : 0;
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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return family >= CHIP_CEDAR ? 4 : 0;
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@@ -358,7 +359,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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case PIPE_CAP_SHAREABLE_SHADERS:
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
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case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
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@@ -8886,6 +8886,105 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
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return 0;
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}
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static int tgsi_pk2h(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bytecode_alu alu;
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int r, i;
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int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
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/* temp.xy = f32_to_f16(src) */
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_FLT32_TO_FLT16;
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alu.dst.chan = 0;
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alu.dst.sel = ctx->temp_reg;
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alu.dst.write = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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alu.dst.chan = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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/* dst.x = temp.y * 0x10000 + temp.x */
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for (i = 0; i < lasti + 1; i++) {
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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continue;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP3_MULADD_UINT24;
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alu.is_op3 = 1;
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tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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alu.last = i == lasti;
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alu.src[0].sel = ctx->temp_reg;
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alu.src[0].chan = 1;
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alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
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alu.src[1].value = 0x10000;
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alu.src[2].sel = ctx->temp_reg;
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alu.src[2].chan = 0;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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return 0;
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}
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static int tgsi_up2h(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bytecode_alu alu;
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int r, i;
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int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
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/* temp.x = src.x */
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/* note: no need to mask out the high bits */
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.chan = 0;
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alu.dst.sel = ctx->temp_reg;
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alu.dst.write = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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/* temp.y = src.x >> 16 */
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP2_LSHR_INT;
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alu.dst.chan = 1;
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alu.dst.sel = ctx->temp_reg;
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alu.dst.write = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
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alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
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alu.src[1].value = 16;
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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/* dst.wz = dst.xy = f16_to_f32(temp.xy) */
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for (i = 0; i < lasti + 1; i++) {
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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continue;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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alu.op = ALU_OP1_FLT16_TO_FLT32;
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alu.src[0].sel = ctx->temp_reg;
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alu.src[0].chan = i % 2;
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alu.last = i == lasti;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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return 0;
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}
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static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
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[TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
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[TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
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@@ -9132,7 +9231,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
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[TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
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[TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
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[TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
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[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
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[TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
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@@ -9147,7 +9246,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
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[TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
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[TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
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[TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
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[TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
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[TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
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@@ -9355,7 +9454,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
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[TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
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[TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
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[TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
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[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
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[TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
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@@ -9370,7 +9469,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
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[TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
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[TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
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[TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
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[TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
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[TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
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