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i965: Actually assign binding table offsets for the TCS.

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As far as I can tell, this was just entirely missing...honestly, I'm
not sure how anything worked at all.

Caught by noticing GPU hangs in image load store tests with scalar TCS,
but probably has broader implications.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
This commit is contained in:
Kenneth Graunke
2016-05-08 21:15:04 -07:00
parent e0e7280db0
commit 5ce405ba0f
1 changed files with 5 additions and 0 deletions
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5
src/mesa/drivers/dri/i965/brw_tcs.c
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@@ -168,6 +168,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,
{
struct gl_context *ctx = &brw->ctx;
const struct brw_compiler *compiler = brw->intelScreen->compiler;
const struct brw_device_info *devinfo = compiler->devinfo;
struct brw_stage_state *stage_state = &brw->tcs.base;
nir_shader *nir;
struct brw_tcs_prog_data prog_data;
@@ -209,6 +210,10 @@ brw_codegen_tcs_prog(struct brw_context *brw,
prog_data.base.base.nr_params = param_count;
if (tcs) {
brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo,
shader_prog, &tcp->program.Base,
&prog_data.base.base, 0);
prog_data.base.base.image_param =
rzalloc_array(NULL, struct brw_image_param, tcs->NumImages);
prog_data.base.base.nr_image_params = tcs->NumImages;