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i965: Port 3DSTATE_INDEX_BUFFER to genxml.

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Also make the brw_get_index_type() function not shift its return, since that
is genxml's job now.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Rafael Antognolli
2017-05-09 17:12:11 -07:00
committed by Kenneth Graunke
parent 71bfb44005
commit 5bbcbabd86
5 changed files with 40 additions and 74 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_context.h
+3 -3
View File
@@ -1398,10 +1398,10 @@ unsigned brw_get_vertex_surface_type(struct brw_context *brw,
static inline unsigned
brw_get_index_type(unsigned index_size)
{
/* The hw needs 0x00000000, 0x00000100, and 0x00000200 for ubyte, ushort,
* and uint, respectively.
/* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
* respectively.
*/
return (index_size >> 1) << 8;
return index_size >> 1;
}
void brw_prepare_vertices(struct brw_context *brw);
src/mesa/drivers/dri/i965/brw_draw_upload.c
-39
View File
@@ -791,42 +791,3 @@ const struct brw_tracked_state brw_indices = {
},
.emit = brw_upload_indices,
};
static void
brw_emit_index_buffer(struct brw_context *brw)
{
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
GLuint cut_index_setting;
if (index_buffer == NULL)
return;
if (brw->prim_restart.enable_cut_index && !brw->is_haswell) {
cut_index_setting = BRW_CUT_INDEX_ENABLE;
} else {
cut_index_setting = 0;
}
BEGIN_BATCH(3);
OUT_BATCH(CMD_INDEX_BUFFER << 16 |
cut_index_setting |
brw_get_index_type(index_buffer->index_size) |
1);
OUT_RELOC(brw->ib.bo,
I915_GEM_DOMAIN_VERTEX, 0,
0);
OUT_RELOC(brw->ib.bo,
I915_GEM_DOMAIN_VERTEX, 0,
brw->ib.size - 1);
ADVANCE_BATCH();
}
const struct brw_tracked_state brw_index_buffer = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_INDEX_BUFFER,
},
.emit = brw_emit_index_buffer,
};
src/mesa/drivers/dri/i965/brw_state.h
-1
View File
@@ -111,7 +111,6 @@ extern const struct brw_tracked_state gen7_depthbuffer;
extern const struct brw_tracked_state gen7_l3_state;
extern const struct brw_tracked_state gen7_push_constant_space;
extern const struct brw_tracked_state gen7_urb;
extern const struct brw_tracked_state gen8_index_buffer;
extern const struct brw_tracked_state gen8_pma_fix;
extern const struct brw_tracked_state gen8_vf_topology;
extern const struct brw_tracked_state brw_cs_work_groups_surface;
src/mesa/drivers/dri/i965/gen8_draw_upload.c
-27
View File
@@ -34,33 +34,6 @@
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
static void
gen8_emit_index_buffer(struct brw_context *brw)
{
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
if (index_buffer == NULL)
return;
BEGIN_BATCH(5);
OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
OUT_BATCH(brw_get_index_type(index_buffer->index_size) | mocs_wb);
OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
OUT_BATCH(brw->ib.size);
ADVANCE_BATCH();
}
const struct brw_tracked_state gen8_index_buffer = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_INDEX_BUFFER,
},
.emit = gen8_emit_index_buffer,
};
static void
gen8_emit_vf_topology(struct brw_context *brw)
{
src/mesa/drivers/dri/i965/genX_state_upload.c
+37 -4
View File
@@ -841,6 +841,39 @@ static const struct brw_tracked_state genX(vertices) = {
.emit = genX(emit_vertices),
};
static void
genX(emit_index_buffer)(struct brw_context *brw)
{
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
if (index_buffer == NULL)
return;
brw_batch_emit(brw, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if GEN_GEN < 8 && !GEN_IS_HASWELL
ib.CutIndexEnable = brw->prim_restart.enable_cut_index;
#endif
ib.IndexFormat = brw_get_index_type(index_buffer->index_size);
ib.BufferStartingAddress = vertex_bo(brw->ib.bo, 0);
#if GEN_GEN >= 8
ib.IndexBufferMOCS = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
ib.BufferSize = brw->ib.size;
#else
ib.BufferEndingAddress = vertex_bo(brw->ib.bo, brw->ib.size - 1);
#endif
}
}
static const struct brw_tracked_state genX(index_buffer) = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_BLORP |
BRW_NEW_INDEX_BUFFER,
},
.emit = genX(emit_index_buffer),
};
#if GEN_IS_HASWELL || GEN_GEN >= 8
static void
genX(upload_cut_index)(struct brw_context *brw)
@@ -4104,7 +4137,7 @@ genX(init_atoms)(struct brw_context *brw)
&genX(drawing_rect),
&brw_indices, /* must come before brw_vertices */
&brw_index_buffer,
&genX(index_buffer),
&genX(vertices),
&brw_constant_buffer
@@ -4171,7 +4204,7 @@ genX(init_atoms)(struct brw_context *brw)
&genX(drawing_rect),
&brw_indices, /* must come before brw_vertices */
&brw_index_buffer,
&genX(index_buffer),
&genX(vertices),
};
#elif GEN_GEN == 7
@@ -4259,7 +4292,7 @@ genX(init_atoms)(struct brw_context *brw)
&genX(drawing_rect),
&brw_indices, /* must come before brw_vertices */
&brw_index_buffer,
&genX(index_buffer),
&genX(vertices),
#if GEN_IS_HASWELL
@@ -4354,7 +4387,7 @@ genX(init_atoms)(struct brw_context *brw)
&gen8_vf_topology,
&brw_indices,
&gen8_index_buffer,
&genX(index_buffer),
&genX(vertices),
&genX(cut_index),