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Nuke the nv0x-nv2x gallium pipe drivers.

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This commit is contained in:
Francisco Jerez
2010-02-04 22:15:22 +01:00
parent bfb5dc68fc
commit 5b6b67eb3f
64 changed files with 8 additions and 8949 deletions
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configure.ac
+1 -1
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@@ -1319,7 +1319,7 @@ AC_ARG_ENABLE([gallium-nouveau],
[enable_gallium_nouveau=no])
if test "x$enable_gallium_nouveau" = xyes; then
GALLIUM_WINSYS_DRM_DIRS="$GALLIUM_WINSYS_DRM_DIRS nouveau"
GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS nouveau nv04 nv10 nv20 nv30 nv40 nv50"
GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS nouveau nv30 nv40 nv50"
fi
dnl
src/gallium/docs/source/distro.rst
-15
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@@ -31,21 +31,6 @@ Wrapper driver.
LLVM Softpipe
^^^^^^^^^^^^^
nVidia nv04
^^^^^^^^^^^
Deprecated.
nVidia nv10
^^^^^^^^^^^
Deprecated.
nVidia nv20
^^^^^^^^^^^
Deprecated.
nVidia nv30
^^^^^^^^^^^
src/gallium/drivers/nouveau/Makefile
+2 -1
View File
@@ -4,6 +4,7 @@ include $(TOP)/configs/current
LIBNAME = nouveau
C_SOURCES = nouveau_screen.c \
nouveau_context.c
nouveau_context.c \
nv04_surface_2d.c
include ../../Makefile.template
src/gallium/drivers/nouveau/nouveau_winsys.h
-18
View File
@@ -26,24 +26,6 @@
/* use along with GPU_WRITE for 2D-only writes */
#define NOUVEAU_BUFFER_USAGE_NO_RENDER (1 << 19)
extern struct pipe_screen *
nv04_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
extern struct pipe_context *
nv04_create(struct pipe_screen *, unsigned pctx_id);
extern struct pipe_screen *
nv10_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
extern struct pipe_context *
nv10_create(struct pipe_screen *, unsigned pctx_id);
extern struct pipe_screen *
nv20_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
extern struct pipe_context *
nv20_create(struct pipe_screen *, unsigned pctx_id);
extern struct pipe_screen *
nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
src/gallium/drivers/nv04/nv04_surface_2d.c → src/gallium/drivers/nouveau/nv04_surface_2d.c
View File
src/gallium/drivers/nv04/nv04_surface_2d.h → src/gallium/drivers/nouveau/nv04_surface_2d.h
View File
src/gallium/drivers/nv04/Makefile
-21
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@@ -1,21 +0,0 @@
TOP = ../../../..
include $(TOP)/configs/current
LIBNAME = nv04
C_SOURCES = \
nv04_surface_2d.c \
nv04_clear.c \
nv04_context.c \
nv04_fragprog.c \
nv04_fragtex.c \
nv04_miptree.c \
nv04_prim_vbuf.c \
nv04_screen.c \
nv04_state.c \
nv04_state_emit.c \
nv04_surface.c \
nv04_transfer.c \
nv04_vbo.c
include ../../Makefile.template
src/gallium/drivers/nv04/nv04_clear.c
-12
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@@ -1,12 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "nv04_context.h"
void
nv04_clear(struct pipe_context *pipe, struct pipe_surface *ps,
unsigned clearValue)
{
pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height, clearValue);
}
src/gallium/drivers/nv04/nv04_context.c
-112
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@@ -1,112 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_defines.h"
#include "util/u_simple_screen.h"
#include "nv04_context.h"
#include "nv04_screen.h"
static void
nv04_flush(struct pipe_context *pipe, unsigned flags,
struct pipe_fence_handle **fence)
{
struct nv04_context *nv04 = nv04_context(pipe);
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
draw_flush(nv04->draw);
FIRE_RING(chan);
if (fence)
*fence = NULL;
}
static void
nv04_destroy(struct pipe_context *pipe)
{
struct nv04_context *nv04 = nv04_context(pipe);
if (nv04->draw)
draw_destroy(nv04->draw);
FREE(nv04);
}
static boolean
nv04_init_hwctx(struct nv04_context *nv04)
{
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
// requires a valid handle
// BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_NOTIFY, 1);
// OUT_RING(0);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_NOP, 1);
OUT_RING(chan, 0);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_CONTROL, 1);
OUT_RING(chan, 0x40182800);
// OUT_RING(1<<20/*no cull*/);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_BLEND, 1);
// OUT_RING(0x24|(1<<6)|(1<<8));
OUT_RING(chan, 0x120001a4);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_FORMAT, 1);
OUT_RING(chan, 0x332213a1);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_FILTER, 1);
OUT_RING(chan, 0x11001010);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_COLORKEY, 1);
OUT_RING(chan, 0x0);
// BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_OFFSET, 1);
// OUT_RING(SCREEN_OFFSET);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_FOGCOLOR, 1);
OUT_RING(chan, 0xff000000);
FIRE_RING (chan);
return TRUE;
}
struct pipe_context *
nv04_create(struct pipe_screen *pscreen, unsigned pctx_id)
{
struct nv04_screen *screen = nv04_screen(pscreen);
struct pipe_winsys *ws = pscreen->winsys;
struct nv04_context *nv04;
struct nouveau_winsys *nvws = screen->nvws;
nv04 = CALLOC(1, sizeof(struct nv04_context));
if (!nv04)
return NULL;
nv04->screen = screen;
nv04->pctx_id = pctx_id;
nv04->nvws = nvws;
nv04->pipe.winsys = ws;
nv04->pipe.screen = pscreen;
nv04->pipe.destroy = nv04_destroy;
nv04->pipe.draw_arrays = nv04_draw_arrays;
nv04->pipe.draw_elements = nv04_draw_elements;
nv04->pipe.clear = nv04_clear;
nv04->pipe.flush = nv04_flush;
nv04->pipe.is_texture_referenced = nouveau_is_texture_referenced;
nv04->pipe.is_buffer_referenced = nouveau_is_buffer_referenced;
nv04_init_surface_functions(nv04);
nv04_init_state_functions(nv04);
nv04->draw = draw_create();
assert(nv04->draw);
draw_wide_point_threshold(nv04->draw, 0.0);
draw_wide_line_threshold(nv04->draw, 0.0);
draw_enable_line_stipple(nv04->draw, FALSE);
draw_enable_point_sprites(nv04->draw, FALSE);
draw_set_rasterize_stage(nv04->draw, nv04_draw_vbuf_stage(nv04));
nv04_init_hwctx(nv04);
return &nv04->pipe;
}
src/gallium/drivers/nv04/nv04_context.h
-151
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@@ -1,151 +0,0 @@
#ifndef __NV04_CONTEXT_H__
#define __NV04_CONTEXT_H__
#include <stdio.h>
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_compiler.h"
#include "util/u_memory.h"
#include "util/u_math.h"
#include "util/u_inlines.h"
#include "draw/draw_vertex.h"
#include "nouveau/nouveau_winsys.h"
#include "nouveau/nouveau_gldefs.h"
#include "nouveau/nouveau_context.h"
#include "nv04_state.h"
#define NOUVEAU_ERR(fmt, args...) \
fprintf(stderr, "%s:%d - "fmt, __func__, __LINE__, ##args);
#define NOUVEAU_MSG(fmt, args...) \
fprintf(stderr, "nouveau: "fmt, ##args);
#include "nv04_screen.h"
#define NV04_NEW_VERTPROG (1 << 1)
#define NV04_NEW_FRAGPROG (1 << 2)
#define NV04_NEW_BLEND (1 << 3)
#define NV04_NEW_RAST (1 << 4)
#define NV04_NEW_CONTROL (1 << 5)
#define NV04_NEW_VIEWPORT (1 << 6)
#define NV04_NEW_SAMPLER (1 << 7)
#define NV04_NEW_FRAMEBUFFER (1 << 8)
#define NV04_NEW_VTXARRAYS (1 << 9)
struct nv04_context {
struct pipe_context pipe;
struct nouveau_winsys *nvws;
struct nv04_screen *screen;
unsigned pctx_id;
struct draw_context *draw;
int chipset;
struct nouveau_notifier *sync;
uint32_t dirty;
struct nv04_blend_state *blend;
struct nv04_sampler_state *sampler[PIPE_MAX_SAMPLERS];
struct nv04_fragtex_state fragtex;
struct nv04_rasterizer_state *rast;
struct nv04_depth_stencil_alpha_state *dsa;
struct nv04_miptree *tex_miptree[PIPE_MAX_SAMPLERS];
unsigned dirty_samplers;
unsigned fp_samplers;
unsigned vp_samplers;
uint32_t rt_enable;
struct pipe_framebuffer_state *framebuffer;
struct pipe_surface *rt;
struct pipe_surface *zeta;
struct {
struct pipe_buffer *buffer;
uint32_t format;
} tex[16];
unsigned vb_enable;
struct {
struct pipe_buffer *buffer;
unsigned delta;
} vb[16];
float *constbuf[PIPE_SHADER_TYPES][32][4];
unsigned constbuf_nr[PIPE_SHADER_TYPES];
struct vertex_info vertex_info;
struct {
struct nouveau_resource *exec_heap;
struct nouveau_resource *data_heap;
struct nv04_vertex_program *active;
struct nv04_vertex_program *current;
struct pipe_buffer *constant_buf;
} vertprog;
struct {
struct nv04_fragment_program *active;
struct nv04_fragment_program *current;
struct pipe_buffer *constant_buf;
} fragprog;
struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
struct pipe_vertex_element vtxelt[PIPE_MAX_ATTRIBS];
struct pipe_viewport_state viewport;
};
static INLINE struct nv04_context *
nv04_context(struct pipe_context *pipe)
{
return (struct nv04_context *)pipe;
}
extern void nv04_init_state_functions(struct nv04_context *nv04);
extern void nv04_init_surface_functions(struct nv04_context *nv04);
extern void nv04_screen_init_miptree_functions(struct pipe_screen *screen);
/* nv04_clear.c */
extern void nv04_clear(struct pipe_context *pipe, struct pipe_surface *ps,
unsigned clearValue);
/* nv04_draw.c */
extern struct draw_stage *nv04_draw_render_stage(struct nv04_context *nv04);
/* nv04_fragprog.c */
extern void nv04_fragprog_bind(struct nv04_context *,
struct nv04_fragment_program *);
extern void nv04_fragprog_destroy(struct nv04_context *,
struct nv04_fragment_program *);
/* nv04_fragtex.c */
extern void nv04_fragtex_bind(struct nv04_context *);
/* nv04_prim_vbuf.c */
struct draw_stage *nv04_draw_vbuf_stage( struct nv04_context *nv04 );
/* nv04_state.c and friends */
extern void nv04_emit_hw_state(struct nv04_context *nv04);
extern void nv04_state_tex_update(struct nv04_context *nv04);
/* nv04_vbo.c */
extern void nv04_draw_arrays(struct pipe_context *, unsigned mode,
unsigned start, unsigned count);
extern void nv04_draw_elements( struct pipe_context *pipe,
struct pipe_buffer *indexBuffer,
unsigned indexSize,
unsigned prim, unsigned start, unsigned count);
#endif
src/gallium/drivers/nv04/nv04_fragprog.c
-21
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@@ -1,21 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_shader_tokens.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_util.h"
#include "nv04_context.h"
void
nv04_fragprog_bind(struct nv04_context *nv04, struct nv04_fragment_program *fp)
{
}
void
nv04_fragprog_destroy(struct nv04_context *nv04,
struct nv04_fragment_program *fp)
{
}
src/gallium/drivers/nv04/nv04_fragtex.c
-73
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@@ -1,73 +0,0 @@
#include "nv04_context.h"
#include "nouveau/nouveau_util.h"
#define _(m,tf) \
{ \
PIPE_FORMAT_##m, \
NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_##tf, \
}
struct nv04_texture_format {
uint pipe;
int format;
};
static struct nv04_texture_format
nv04_texture_formats[] = {
_(A8R8G8B8_UNORM, A8R8G8B8),
_(X8R8G8B8_UNORM, X8R8G8B8),
_(A1R5G5B5_UNORM, A1R5G5B5),
_(A4R4G4B4_UNORM, A4R4G4B4),
_(L8_UNORM, Y8 ),
_(A8_UNORM, Y8 ),
};
static uint32_t
nv04_fragtex_format(uint pipe_format)
{
struct nv04_texture_format *tf = nv04_texture_formats;
int i;
for (i=0; i< sizeof(nv04_texture_formats)/sizeof(nv04_texture_formats[0]); i++) {
if (tf->pipe == pipe_format)
return tf->format;
tf++;
}
NOUVEAU_ERR("unknown texture format %s\n", pf_name(pipe_format));
return 0;
}
static void
nv04_fragtex_build(struct nv04_context *nv04, int unit)
{
struct nv04_miptree *nv04mt = nv04->tex_miptree[unit];
struct pipe_texture *pt = &nv04mt->base;
switch (pt->target) {
case PIPE_TEXTURE_2D:
break;
default:
NOUVEAU_ERR("Unknown target %d\n", pt->target);
return;
}
nv04->fragtex.format = NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER
| NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER
| nv04_fragtex_format(pt->format)
| ( (pt->last_level + 1) << NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT )
| ( log2i(pt->width0) << NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT )
| ( log2i(pt->height0) << NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT )
| NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE
| NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE
;
}
void
nv04_fragtex_bind(struct nv04_context *nv04)
{
nv04_fragtex_build(nv04, 0);
}
src/gallium/drivers/nv04/nv04_miptree.c
-146
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@@ -1,146 +0,0 @@
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "util/u_inlines.h"
#include "util/u_math.h"
#include "nv04_context.h"
#include "nv04_screen.h"
static void
nv04_miptree_layout(struct nv04_miptree *nv04mt)
{
struct pipe_texture *pt = &nv04mt->base;
uint offset = 0;
int nr_faces, l;
nr_faces = 1;
for (l = 0; l <= pt->last_level; l++) {
nv04mt->level[l].pitch = pt->width0;
nv04mt->level[l].pitch = (nv04mt->level[l].pitch + 63) & ~63;
}
for (l = 0; l <= pt->last_level; l++) {
nv04mt->level[l].image_offset =
CALLOC(nr_faces, sizeof(unsigned));
/* XXX guess was obviously missing */
nv04mt->level[l].image_offset[0] = offset;
offset += nv04mt->level[l].pitch * u_minify(pt->height0, l);
}
nv04mt->total_size = offset;
}
static struct pipe_texture *
nv04_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
{
struct nv04_miptree *mt;
mt = MALLOC(sizeof(struct nv04_miptree));
if (!mt)
return NULL;
mt->base = *pt;
pipe_reference_init(&mt->base.reference, 1);
mt->base.screen = pscreen;
//mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
nv04_miptree_layout(mt);
mt->buffer = pscreen->buffer_create(pscreen, 256, PIPE_BUFFER_USAGE_PIXEL |
NOUVEAU_BUFFER_USAGE_TEXTURE,
mt->total_size);
if (!mt->buffer) {
printf("failed %d byte alloc\n",mt->total_size);
FREE(mt);
return NULL;
}
mt->bo = nouveau_bo(mt->buffer);
return &mt->base;
}
static struct pipe_texture *
nv04_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
const unsigned *stride, struct pipe_buffer *pb)
{
struct nv04_miptree *mt;
/* Only supports 2D, non-mipmapped textures for the moment */
if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
pt->depth0 != 1)
return NULL;
mt = CALLOC_STRUCT(nv04_miptree);
if (!mt)
return NULL;
mt->base = *pt;
pipe_reference_init(&mt->base.reference, 1);
mt->base.screen = pscreen;
mt->level[0].pitch = stride[0];
mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
pipe_buffer_reference(&mt->buffer, pb);
mt->bo = nouveau_bo(mt->buffer);
return &mt->base;
}
static void
nv04_miptree_destroy(struct pipe_texture *pt)
{
struct nv04_miptree *mt = (struct nv04_miptree *)pt;
int l;
pipe_buffer_reference(&mt->buffer, NULL);
for (l = 0; l <= pt->last_level; l++) {
if (mt->level[l].image_offset)
FREE(mt->level[l].image_offset);
}
FREE(mt);
}
static struct pipe_surface *
nv04_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_texture *pt,
unsigned face, unsigned level, unsigned zslice,
unsigned flags)
{
struct nv04_miptree *nv04mt = (struct nv04_miptree *)pt;
struct nv04_surface *ns;
ns = CALLOC_STRUCT(nv04_surface);
if (!ns)
return NULL;
pipe_texture_reference(&ns->base.texture, pt);
ns->base.format = pt->format;
ns->base.width = u_minify(pt->width0, level);
ns->base.height = u_minify(pt->height0, level);
ns->base.usage = flags;
pipe_reference_init(&ns->base.reference, 1);
ns->base.face = face;
ns->base.level = level;
ns->base.zslice = zslice;
ns->pitch = nv04mt->level[level].pitch;
ns->base.offset = nv04mt->level[level].image_offset[0];
return &ns->base;
}
static void
nv04_miptree_surface_del(struct pipe_surface *ps)
{
pipe_texture_reference(&ps->texture, NULL);
FREE(ps);
}
void
nv04_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv04_miptree_create;
pscreen->texture_blanket = nv04_miptree_blanket;
pscreen->texture_destroy = nv04_miptree_destroy;
pscreen->get_tex_surface = nv04_miptree_surface_new;
pscreen->tex_surface_destroy = nv04_miptree_surface_del;
}
src/gallium/drivers/nv04/nv04_prim_vbuf.c
-339
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@@ -1,339 +0,0 @@
#include "util/u_debug.h"
#include "util/u_inlines.h"
#include "util/u_simple_screen.h"
#include "pipe/p_compiler.h"
#include "draw/draw_vbuf.h"
#include "nv04_context.h"
#include "nv04_state.h"
#define VERTEX_SIZE 40
#define VERTEX_BUFFER_SIZE (4096*VERTEX_SIZE) // 4096 vertices of 40 bytes each
/**
* Primitive renderer for nv04.
*/
struct nv04_vbuf_render {
struct vbuf_render base;
struct nv04_context *nv04;
/** Vertex buffer */
unsigned char* buffer;
/** Vertex size in bytes */
unsigned vertex_size;
/** Current primitive */
unsigned prim;
};
/**
* Basically a cast wrapper.
*/
static INLINE struct nv04_vbuf_render *
nv04_vbuf_render( struct vbuf_render *render )
{
assert(render);
return (struct nv04_vbuf_render *)render;
}
static const struct vertex_info *
nv04_vbuf_render_get_vertex_info( struct vbuf_render *render )
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
struct nv04_context *nv04 = nv04_render->nv04;
return &nv04->vertex_info;
}
static boolean
nv04_vbuf_render_allocate_vertices( struct vbuf_render *render,
ushort vertex_size,
ushort nr_vertices )
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
nv04_render->buffer = (unsigned char*) MALLOC(VERTEX_BUFFER_SIZE);
assert(!nv04_render->buffer);
return nv04_render->buffer ? TRUE : FALSE;
}
static void *
nv04_vbuf_render_map_vertices( struct vbuf_render *render )
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
return nv04_render->buffer;
}
static void
nv04_vbuf_render_unmap_vertices( struct vbuf_render *render,
ushort min_index,
ushort max_index )
{
}
static boolean
nv04_vbuf_render_set_primitive( struct vbuf_render *render,
unsigned prim )
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
if (prim <= PIPE_PRIM_LINE_STRIP)
return FALSE;
nv04_render->prim = prim;
return TRUE;
}
static INLINE void nv04_2triangles(struct nv04_context* nv04, unsigned char* buffer, ushort v0, ushort v1, ushort v2, ushort v3, ushort v4, ushort v5)
{
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0xA), 49);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v0,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v1,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v2,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v3,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v4,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v5,8);
OUT_RING(chan, 0xFEDCBA);
}
static INLINE void nv04_1triangle(struct nv04_context* nv04, unsigned char* buffer, ushort v0, ushort v1, ushort v2)
{
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0xD), 25);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v0,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v1,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v2,8);
OUT_RING(chan, 0xFED);
}
static INLINE void nv04_1quad(struct nv04_context* nv04, unsigned char* buffer, ushort v0, ushort v1, ushort v2, ushort v3)
{
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0xC), 33);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v0,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v1,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v2,8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * v3,8);
OUT_RING(chan, 0xFECEDC);
}
static void nv04_vbuf_render_triangles_elts(struct nv04_vbuf_render * render, const ushort * indices, uint nr_indices)
{
unsigned char* buffer = render->buffer;
struct nv04_context* nv04 = render->nv04;
int i;
for( i=0; i< nr_indices-5; i+=6)
nv04_2triangles(nv04,
buffer,
indices[i+0],
indices[i+1],
indices[i+2],
indices[i+3],
indices[i+4],
indices[i+5]
);
if (i != nr_indices)
{
nv04_1triangle(nv04,
buffer,
indices[i+0],
indices[i+1],
indices[i+2]
);
i+=3;
}
if (i != nr_indices)
NOUVEAU_ERR("Houston, we have lost some vertices\n");
}
static void nv04_vbuf_render_tri_strip_elts(struct nv04_vbuf_render* render, const ushort* indices, uint nr_indices)
{
const uint32_t striptbl[]={0x321210,0x543432,0x765654,0x987876,0xBA9A98,0xDCBCBA,0xFEDEDC};
unsigned char* buffer = render->buffer;
struct nv04_context *nv04 = render->nv04;
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
int i,j;
for(i = 0; i<nr_indices; i+=14)
{
int numvert = MIN2(16, nr_indices - i);
int numtri = numvert - 2;
if (numvert<3)
break;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0), numvert*8);
for(j = 0; j<numvert; j++)
OUT_RINGp(chan, buffer + VERTEX_SIZE * indices [i+j], 8 );
BEGIN_RING_NI(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(0), (numtri+1)/2 );
for(j = 0; j<numtri/2; j++ )
OUT_RING(chan, striptbl[j]);
if (numtri%2)
OUT_RING(chan, striptbl[numtri/2]&0xFFF);
}
}
static void nv04_vbuf_render_tri_fan_elts(struct nv04_vbuf_render* render, const ushort* indices, uint nr_indices)
{
const uint32_t fantbl[]={0x320210,0x540430,0x760650,0x980870,0xBA0A90,0xDC0CB0,0xFE0ED0};
unsigned char* buffer = render->buffer;
struct nv04_context *nv04 = render->nv04;
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
int i,j;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0), 8);
OUT_RINGp(chan, buffer + VERTEX_SIZE * indices[0], 8);
for(i = 1; i<nr_indices; i+=14)
{
int numvert=MIN2(15, nr_indices - i);
int numtri=numvert-2;
if (numvert < 3)
break;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(0x1), numvert*8);
for(j=0;j<numvert;j++)
OUT_RINGp(chan, buffer + VERTEX_SIZE * indices[ i+j ], 8 );
BEGIN_RING_NI(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(0), (numtri+1)/2);
for(j = 0; j<numtri/2; j++)
OUT_RING(chan, fantbl[j]);
if (numtri%2)
OUT_RING(chan, fantbl[numtri/2]&0xFFF);
}
}
static void nv04_vbuf_render_quads_elts(struct nv04_vbuf_render* render, const ushort* indices, uint nr_indices)
{
unsigned char* buffer = render->buffer;
struct nv04_context* nv04 = render->nv04;
int i;
for(i = 0; i < nr_indices; i += 4)
nv04_1quad(nv04,
buffer,
indices[i+0],
indices[i+1],
indices[i+2],
indices[i+3]
);
}
static void
nv04_vbuf_render_draw( struct vbuf_render *render,
const ushort *indices,
uint nr_indices)
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
// emit the indices
switch( nv04_render->prim )
{
case PIPE_PRIM_TRIANGLES:
nv04_vbuf_render_triangles_elts(nv04_render, indices, nr_indices);
break;
case PIPE_PRIM_QUAD_STRIP:
case PIPE_PRIM_TRIANGLE_STRIP:
nv04_vbuf_render_tri_strip_elts(nv04_render, indices, nr_indices);
break;
case PIPE_PRIM_TRIANGLE_FAN:
case PIPE_PRIM_POLYGON:
nv04_vbuf_render_tri_fan_elts(nv04_render, indices, nr_indices);
break;
case PIPE_PRIM_QUADS:
nv04_vbuf_render_quads_elts(nv04_render, indices, nr_indices);
break;
default:
NOUVEAU_ERR("You have to implement primitive %d, young padawan\n", nv04_render->prim);
break;
}
}
static void
nv04_vbuf_render_release_vertices( struct vbuf_render *render )
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
free(nv04_render->buffer);
nv04_render->buffer = NULL;
}
static void
nv04_vbuf_render_destroy( struct vbuf_render *render )
{
struct nv04_vbuf_render *nv04_render = nv04_vbuf_render(render);
FREE(nv04_render);
}
/**
* Create a new primitive render.
*/
static struct vbuf_render *
nv04_vbuf_render_create( struct nv04_context *nv04 )
{
struct nv04_vbuf_render *nv04_render = CALLOC_STRUCT(nv04_vbuf_render);
nv04_render->nv04 = nv04;
nv04_render->base.max_vertex_buffer_bytes = VERTEX_BUFFER_SIZE;
nv04_render->base.max_indices = 65536;
nv04_render->base.get_vertex_info = nv04_vbuf_render_get_vertex_info;
nv04_render->base.allocate_vertices = nv04_vbuf_render_allocate_vertices;
nv04_render->base.map_vertices = nv04_vbuf_render_map_vertices;
nv04_render->base.unmap_vertices = nv04_vbuf_render_unmap_vertices;
nv04_render->base.set_primitive = nv04_vbuf_render_set_primitive;
nv04_render->base.draw = nv04_vbuf_render_draw;
nv04_render->base.release_vertices = nv04_vbuf_render_release_vertices;
nv04_render->base.destroy = nv04_vbuf_render_destroy;
return &nv04_render->base;
}
/**
* Create a new primitive vbuf/render stage.
*/
struct draw_stage *nv04_draw_vbuf_stage( struct nv04_context *nv04 )
{
struct vbuf_render *render;
struct draw_stage *stage;
render = nv04_vbuf_render_create(nv04);
if(!render)
return NULL;
stage = draw_vbuf_stage( nv04->draw, render );
if(!stage) {
render->destroy(render);
return NULL;
}
return stage;
}
src/gallium/drivers/nv04/nv04_screen.c
-222
View File
@@ -1,222 +0,0 @@
#include "pipe/p_screen.h"
#include "util/u_inlines.h"
#include "nv04_context.h"
#include "nv04_screen.h"
static int
nv04_screen_get_param(struct pipe_screen *screen, int param)
{
switch (param) {
case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
return 1;
case PIPE_CAP_NPOT_TEXTURES:
return 0;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 0;
case PIPE_CAP_GLSL:
return 0;
case PIPE_CAP_ANISOTROPIC_FILTER:
return 0;
case PIPE_CAP_POINT_SPRITE:
return 0;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 1;
case PIPE_CAP_OCCLUSION_QUERY:
return 0;
case PIPE_CAP_TEXTURE_SHADOW_MAP:
return 0;
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
return 10;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 0;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 0;
case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
return 0;
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
return 0;
case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
return 1;
case PIPE_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
return 0;
case NOUVEAU_CAP_HW_VTXBUF:
case NOUVEAU_CAP_HW_IDXBUF:
return 0;
case PIPE_CAP_INDEP_BLEND_ENABLE:
return 0;
case PIPE_CAP_INDEP_BLEND_FUNC:
return 0;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
return 1;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
}
}
static float
nv04_screen_get_paramf(struct pipe_screen *screen, int param)
{
switch (param) {
case PIPE_CAP_MAX_LINE_WIDTH:
case PIPE_CAP_MAX_LINE_WIDTH_AA:
return 0.0;
case PIPE_CAP_MAX_POINT_WIDTH:
case PIPE_CAP_MAX_POINT_WIDTH_AA:
return 0.0;
case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
return 0.0;
case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
return 0.0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0.0;
}
}
static boolean
nv04_screen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
unsigned tex_usage, unsigned geom_flags)
{
if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
return TRUE;
default:
break;
}
} else
if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
switch (format) {
case PIPE_FORMAT_Z16_UNORM:
return TRUE;
default:
break;
}
} else {
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
case PIPE_FORMAT_A1R5G5B5_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
case PIPE_FORMAT_L8_UNORM:
case PIPE_FORMAT_A8_UNORM:
return TRUE;
default:
break;
}
}
return FALSE;
}
static void
nv04_screen_destroy(struct pipe_screen *pscreen)
{
struct nv04_screen *screen = nv04_screen(pscreen);
nouveau_notifier_free(&screen->sync);
nouveau_grobj_free(&screen->fahrenheit);
nv04_surface_2d_takedown(&screen->eng2d);
nouveau_screen_fini(&screen->base);
FREE(pscreen);
}
static struct pipe_buffer *
nv04_surface_buffer(struct pipe_surface *surf)
{
struct nv04_miptree *mt = (struct nv04_miptree *)surf->texture;
return mt->buffer;
}
struct pipe_screen *
nv04_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
{
struct nv04_screen *screen = CALLOC_STRUCT(nv04_screen);
struct nouveau_channel *chan;
struct pipe_screen *pscreen;
unsigned fahrenheit_class = 0, sub3d_class = 0;
int ret;
if (!screen)
return NULL;
pscreen = &screen->base.base;
ret = nouveau_screen_init(&screen->base, dev);
if (ret) {
nv04_screen_destroy(pscreen);
return NULL;
}
chan = screen->base.channel;
pscreen->winsys = ws;
pscreen->destroy = nv04_screen_destroy;
pscreen->get_param = nv04_screen_get_param;
pscreen->get_paramf = nv04_screen_get_paramf;
pscreen->is_format_supported = nv04_screen_is_format_supported;
nv04_screen_init_miptree_functions(pscreen);
nv04_screen_init_transfer_functions(pscreen);
if (dev->chipset >= 0x20) {
fahrenheit_class = 0;
sub3d_class = 0;
} else if (dev->chipset >= 0x10) {
fahrenheit_class = NV10_TEXTURED_TRIANGLE;
sub3d_class = NV10_CONTEXT_SURFACES_3D;
} else {
fahrenheit_class=NV04_TEXTURED_TRIANGLE;
sub3d_class = NV04_CONTEXT_SURFACES_3D;
}
if (!fahrenheit_class) {
NOUVEAU_ERR("Unknown nv04 chipset: nv%02x\n", dev->chipset);
return NULL;
}
/* 3D object */
ret = nouveau_grobj_alloc(chan, 0xbeef0001, fahrenheit_class,
&screen->fahrenheit);
if (ret) {
NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
return NULL;
}
BIND_RING(chan, screen->fahrenheit, 7);
/* 3D surface object */
ret = nouveau_grobj_alloc(chan, 0xbeef0002, sub3d_class,
&screen->context_surfaces_3d);
if (ret) {
NOUVEAU_ERR("Error creating 3D surface object: %d\n", ret);
return NULL;
}
BIND_RING(chan, screen->context_surfaces_3d, 6);
/* 2D engine setup */
screen->eng2d = nv04_surface_2d_init(&screen->base);
screen->eng2d->buf = nv04_surface_buffer;
/* Notifier for sync purposes */
ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
if (ret) {
NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
nv04_screen_destroy(pscreen);
return NULL;
}
return pscreen;
}
src/gallium/drivers/nv04/nv04_screen.h
-30
View File
@@ -1,30 +0,0 @@
#ifndef __NV04_SCREEN_H__
#define __NV04_SCREEN_H__
#include "nouveau/nouveau_screen.h"
#include "nv04_surface_2d.h"
struct nv04_screen {
struct nouveau_screen base;
struct nouveau_winsys *nvws;
unsigned chipset;
/* HW graphics objects */
struct nv04_surface_2d *eng2d;
struct nouveau_grobj *fahrenheit;
struct nouveau_grobj *context_surfaces_3d;
struct nouveau_notifier *sync;
};
static INLINE struct nv04_screen *
nv04_screen(struct pipe_screen *screen)
{
return (struct nv04_screen *)screen;
}
void
nv04_screen_init_transfer_functions(struct pipe_screen *pscreen);
#endif
src/gallium/drivers/nv04/nv04_state.c
-459
View File
@@ -1,459 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "pipe/p_shader_tokens.h"
#include "util/u_inlines.h"
#include "tgsi/tgsi_parse.h"
#include "nv04_context.h"
#include "nv04_state.h"
static void *
nv04_blend_state_create(struct pipe_context *pipe,
const struct pipe_blend_state *cso)
{
struct nv04_blend_state *cb;
cb = MALLOC(sizeof(struct nv04_blend_state));
cb->b_enable = cso->rt[0].blend_enable ? 1 : 0;
cb->b_src = ((nvgl_blend_func(cso->rt[0].alpha_src_factor)<<16) |
(nvgl_blend_func(cso->rt[0].rgb_src_factor)));
cb->b_dst = ((nvgl_blend_func(cso->rt[0].alpha_dst_factor)<<16) |
(nvgl_blend_func(cso->rt[0].rgb_dst_factor)));
return (void *)cb;
}
static void
nv04_blend_state_bind(struct pipe_context *pipe, void *blend)
{
struct nv04_context *nv04 = nv04_context(pipe);
nv04->blend = (struct nv04_blend_state*)blend;
nv04->dirty |= NV04_NEW_BLEND;
}
static void
nv04_blend_state_delete(struct pipe_context *pipe, void *hwcso)
{
free(hwcso);
}
static INLINE unsigned
wrap_mode(unsigned wrap) {
unsigned ret;
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT;
break;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT;
break;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_CLAMP:
ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP:
default:
NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
ret = NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP;
}
return ret >> NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT;
}
static void *
nv04_sampler_state_create(struct pipe_context *pipe,
const struct pipe_sampler_state *cso)
{
struct nv04_sampler_state *ss;
uint32_t filter = 0;
ss = MALLOC(sizeof(struct nv04_sampler_state));
ss->format = ((wrap_mode(cso->wrap_s) << NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT) |
(wrap_mode(cso->wrap_t) << NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT));
if (cso->max_anisotropy > 1.0) {
filter |= NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE | NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE;
}
switch (cso->mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST;
break;
}
switch (cso->min_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR;
break;
}
break;
case PIPE_TEX_FILTER_NEAREST:
default:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST;
break;
}
break;
}
ss->filter = filter;
return (void *)ss;
}
static void
nv04_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
{
struct nv04_context *nv04 = nv04_context(pipe);
unsigned unit;
for (unit = 0; unit < nr; unit++) {
nv04->sampler[unit] = sampler[unit];
nv04->dirty_samplers |= (1 << unit);
}
}
static void
nv04_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
{
free(hwcso);
}
static void
nv04_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
struct pipe_texture **miptree)
{
struct nv04_context *nv04 = nv04_context(pipe);
unsigned unit;
for (unit = 0; unit < nr; unit++) {
nv04->tex_miptree[unit] = (struct nv04_miptree *)miptree[unit];
nv04->dirty_samplers |= (1 << unit);
}
}
static void *
nv04_rasterizer_state_create(struct pipe_context *pipe,
const struct pipe_rasterizer_state *cso)
{
struct nv04_rasterizer_state *rs;
/*XXX: ignored:
* scissor
* points/lines (no hw support, emulated with tris in gallium)
*/
rs = MALLOC(sizeof(struct nv04_rasterizer_state));
rs->blend = cso->flatshade ? NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT : NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD;
return (void *)rs;
}
static void
nv04_rasterizer_state_bind(struct pipe_context *pipe, void *rast)
{
struct nv04_context *nv04 = nv04_context(pipe);
nv04->rast = (struct nv04_rasterizer_state*)rast;
draw_set_rasterizer_state(nv04->draw, (nv04->rast ? nv04->rast->templ : NULL));
nv04->dirty |= NV04_NEW_RAST | NV04_NEW_BLEND;
}
static void
nv04_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
{
free(hwcso);
}
static INLINE uint32_t nv04_compare_func(uint32_t f)
{
switch ( f ) {
case PIPE_FUNC_NEVER: return 1;
case PIPE_FUNC_LESS: return 2;
case PIPE_FUNC_EQUAL: return 3;
case PIPE_FUNC_LEQUAL: return 4;
case PIPE_FUNC_GREATER: return 5;
case PIPE_FUNC_NOTEQUAL: return 6;
case PIPE_FUNC_GEQUAL: return 7;
case PIPE_FUNC_ALWAYS: return 8;
}
NOUVEAU_MSG("Unable to find the function\n");
return 0;
}
static void *
nv04_depth_stencil_alpha_state_create(struct pipe_context *pipe,
const struct pipe_depth_stencil_alpha_state *cso)
{
struct nv04_depth_stencil_alpha_state *hw;
hw = MALLOC(sizeof(struct nv04_depth_stencil_alpha_state));
hw->control = float_to_ubyte(cso->alpha.ref_value);
hw->control |= ( nv04_compare_func(cso->alpha.func) << NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT );
hw->control |= cso->alpha.enabled ? NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE : 0;
hw->control |= NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN;
hw->control |= cso->depth.enabled ? NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE : 0;
hw->control |= ( nv04_compare_func(cso->depth.func)<< NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT );
hw->control |= 1 << NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT; // no culling, handled by the draw module
hw->control |= NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE;
hw->control |= NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE;
hw->control |= cso->depth.writemask ? NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE : 0;
hw->control |= 1 << NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT; // integer zbuffer format
return (void *)hw;
}
static void
nv04_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
{
struct nv04_context *nv04 = nv04_context(pipe);
nv04->dsa = hwcso;
nv04->dirty |= NV04_NEW_CONTROL;
}
static void
nv04_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
{
free(hwcso);
}
static void *
nv04_vp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *templ)
{
struct nv04_context *nv04 = nv04_context(pipe);
return draw_create_vertex_shader(nv04->draw, templ);
}
static void
nv04_vp_state_bind(struct pipe_context *pipe, void *shader)
{
struct nv04_context *nv04 = nv04_context(pipe);
draw_bind_vertex_shader(nv04->draw, (struct draw_vertex_shader *) shader);
nv04->dirty |= NV04_NEW_VERTPROG;
}
static void
nv04_vp_state_delete(struct pipe_context *pipe, void *shader)
{
struct nv04_context *nv04 = nv04_context(pipe);
draw_delete_vertex_shader(nv04->draw, (struct draw_vertex_shader *) shader);
}
static void *
nv04_fp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
struct nv04_fragment_program *fp;
fp = CALLOC(1, sizeof(struct nv04_fragment_program));
fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
return (void *)fp;
}
static void
nv04_fp_state_bind(struct pipe_context *pipe, void *hwcso)
{
struct nv04_context *nv04 = nv04_context(pipe);
struct nv04_fragment_program *fp = hwcso;
nv04->fragprog.current = fp;
nv04->dirty |= NV04_NEW_FRAGPROG;
}
static void
nv04_fp_state_delete(struct pipe_context *pipe, void *hwcso)
{
struct nv04_context *nv04 = nv04_context(pipe);
struct nv04_fragment_program *fp = hwcso;
nv04_fragprog_destroy(nv04, fp);
free((void*)fp->pipe.tokens);
free(fp);
}
static void
nv04_set_blend_color(struct pipe_context *pipe,
const struct pipe_blend_color *bcol)
{
}
static void
nv04_set_clip_state(struct pipe_context *pipe,
const struct pipe_clip_state *clip)
{
}
static void
nv04_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
struct pipe_buffer *buf )
{
struct nv04_context *nv04 = nv04_context(pipe);
struct pipe_screen *pscreen = pipe->screen;
assert(shader < PIPE_SHADER_TYPES);
assert(index == 0);
if (buf) {
void *mapped;
if (buf && buf->size &&
(mapped = pipe_buffer_map(pscreen, buf, PIPE_BUFFER_USAGE_CPU_READ)))
{
memcpy(nv04->constbuf[shader], mapped, buf->size);
nv04->constbuf_nr[shader] =
buf->size / (4 * sizeof(float));
pipe_buffer_unmap(pscreen, buf);
}
}
}
static void
nv04_set_framebuffer_state(struct pipe_context *pipe,
const struct pipe_framebuffer_state *fb)
{
struct nv04_context *nv04 = nv04_context(pipe);
nv04->framebuffer = (struct pipe_framebuffer_state*)fb;
nv04->dirty |= NV04_NEW_FRAMEBUFFER;
}
static void
nv04_set_polygon_stipple(struct pipe_context *pipe,
const struct pipe_poly_stipple *stipple)
{
NOUVEAU_ERR("line stipple hahaha\n");
}
static void
nv04_set_scissor_state(struct pipe_context *pipe,
const struct pipe_scissor_state *s)
{
/* struct nv04_context *nv04 = nv04_context(pipe);
// XXX
BEGIN_RING(fahrenheit, NV04_TEXTURED_TRIANGLE_SCISSOR_HORIZ, 2);
OUT_RING (((s->maxx - s->minx) << 16) | s->minx);
OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/
}
static void
nv04_set_viewport_state(struct pipe_context *pipe,
const struct pipe_viewport_state *viewport)
{
struct nv04_context *nv04 = nv04_context(pipe);
nv04->viewport = *viewport;
draw_set_viewport_state(nv04->draw, &nv04->viewport);
}
static void
nv04_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
const struct pipe_vertex_buffer *buffers)
{
struct nv04_context *nv04 = nv04_context(pipe);
memcpy(nv04->vtxbuf, buffers, count * sizeof(buffers[0]));
nv04->dirty |= NV04_NEW_VTXARRAYS;
draw_set_vertex_buffers(nv04->draw, count, buffers);
}
static void
nv04_set_vertex_elements(struct pipe_context *pipe, unsigned count,
const struct pipe_vertex_element *elements)
{
struct nv04_context *nv04 = nv04_context(pipe);
memcpy(nv04->vtxelt, elements, sizeof(*elements) * count);
nv04->dirty |= NV04_NEW_VTXARRAYS;
draw_set_vertex_elements(nv04->draw, count, elements);
}
void
nv04_init_state_functions(struct nv04_context *nv04)
{
nv04->pipe.create_blend_state = nv04_blend_state_create;
nv04->pipe.bind_blend_state = nv04_blend_state_bind;
nv04->pipe.delete_blend_state = nv04_blend_state_delete;
nv04->pipe.create_sampler_state = nv04_sampler_state_create;
nv04->pipe.bind_fragment_sampler_states = nv04_sampler_state_bind;
nv04->pipe.delete_sampler_state = nv04_sampler_state_delete;
nv04->pipe.set_fragment_sampler_textures = nv04_set_sampler_texture;
nv04->pipe.create_rasterizer_state = nv04_rasterizer_state_create;
nv04->pipe.bind_rasterizer_state = nv04_rasterizer_state_bind;
nv04->pipe.delete_rasterizer_state = nv04_rasterizer_state_delete;
nv04->pipe.create_depth_stencil_alpha_state = nv04_depth_stencil_alpha_state_create;
nv04->pipe.bind_depth_stencil_alpha_state = nv04_depth_stencil_alpha_state_bind;
nv04->pipe.delete_depth_stencil_alpha_state = nv04_depth_stencil_alpha_state_delete;
nv04->pipe.create_vs_state = nv04_vp_state_create;
nv04->pipe.bind_vs_state = nv04_vp_state_bind;
nv04->pipe.delete_vs_state = nv04_vp_state_delete;
nv04->pipe.create_fs_state = nv04_fp_state_create;
nv04->pipe.bind_fs_state = nv04_fp_state_bind;
nv04->pipe.delete_fs_state = nv04_fp_state_delete;
nv04->pipe.set_blend_color = nv04_set_blend_color;
nv04->pipe.set_clip_state = nv04_set_clip_state;
nv04->pipe.set_constant_buffer = nv04_set_constant_buffer;
nv04->pipe.set_framebuffer_state = nv04_set_framebuffer_state;
nv04->pipe.set_polygon_stipple = nv04_set_polygon_stipple;
nv04->pipe.set_scissor_state = nv04_set_scissor_state;
nv04->pipe.set_viewport_state = nv04_set_viewport_state;
nv04->pipe.set_vertex_buffers = nv04_set_vertex_buffers;
nv04->pipe.set_vertex_elements = nv04_set_vertex_elements;
}
src/gallium/drivers/nv04/nv04_state.h
-72
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@@ -1,72 +0,0 @@
#ifndef __NV04_STATE_H__
#define __NV04_STATE_H__
#include "pipe/p_state.h"
#include "tgsi/tgsi_scan.h"
struct nv04_blend_state {
uint32_t b_enable;
uint32_t b_src;
uint32_t b_dst;
};
struct nv04_fragtex_state {
uint32_t format;
};
struct nv04_sampler_state {
uint32_t filter;
uint32_t format;
};
struct nv04_depth_stencil_alpha_state {
uint32_t control;
};
struct nv04_rasterizer_state {
uint32_t blend;
const struct pipe_rasterizer_state *templ;
};
struct nv04_miptree {
struct pipe_texture base;
struct nouveau_bo *bo;
struct pipe_buffer *buffer;
uint total_size;
struct {
uint pitch;
uint *image_offset;
} level[PIPE_MAX_TEXTURE_LEVELS];
};
struct nv04_fragment_program_data {
unsigned offset;
unsigned index;
};
struct nv04_fragment_program {
struct pipe_shader_state pipe;
struct tgsi_shader_info info;
boolean translated;
boolean on_hw;
unsigned samplers;
uint32_t *insn;
int insn_len;
struct nv04_fragment_program_data *consts;
unsigned nr_consts;
struct pipe_buffer *buffer;
uint32_t fp_control;
uint32_t fp_reg_control;
};
#endif
src/gallium/drivers/nv04/nv04_state_emit.c
-246
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@@ -1,246 +0,0 @@
#include "nv04_context.h"
#include "nv04_state.h"
static void nv04_vertex_layout(struct pipe_context* pipe)
{
struct nv04_context *nv04 = nv04_context(pipe);
struct nv04_fragment_program *fp = nv04->fragprog.current;
uint32_t src = 0;
int i;
struct vertex_info vinfo;
memset(&vinfo, 0, sizeof(vinfo));
for (i = 0; i < fp->info.num_inputs; i++) {
int isn = fp->info.input_semantic_name[i];
int isi = fp->info.input_semantic_index[i];
switch (isn) {
case TGSI_SEMANTIC_POSITION:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR, src++);
break;
case TGSI_SEMANTIC_COLOR:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR, src++);
break;
default:
case TGSI_SEMANTIC_GENERIC:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE, src++);
break;
case TGSI_SEMANTIC_FOG:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE, src++);
break;
}
}
printf("%d vertex input\n",fp->info.num_inputs);
draw_compute_vertex_size(&vinfo);
}
static uint32_t nv04_blend_func(uint32_t f)
{
switch ( f ) {
case PIPE_BLENDFACTOR_ZERO: return 0x1;
case PIPE_BLENDFACTOR_ONE: return 0x2;
case PIPE_BLENDFACTOR_SRC_COLOR: return 0x3;
case PIPE_BLENDFACTOR_INV_SRC_COLOR: return 0x4;
case PIPE_BLENDFACTOR_SRC_ALPHA: return 0x5;
case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return 0x6;
case PIPE_BLENDFACTOR_DST_ALPHA: return 0x7;
case PIPE_BLENDFACTOR_INV_DST_ALPHA: return 0x8;
case PIPE_BLENDFACTOR_DST_COLOR: return 0x9;
case PIPE_BLENDFACTOR_INV_DST_COLOR: return 0xA;
case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return 0xB;
}
NOUVEAU_MSG("Unable to find the blend function 0x%x\n",f);
return 0;
}
static void nv04_emit_control(struct nv04_context* nv04)
{
uint32_t control = nv04->dsa->control;
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_CONTROL, 1);
OUT_RING(chan, control);
}
static void nv04_emit_blend(struct nv04_context* nv04)
{
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
uint32_t blend;
blend=0x4; // texture MODULATE_ALPHA
blend|=0x20; // alpha is MSB
blend|=(2<<6); // flat shading
blend|=(1<<8); // persp correct
blend|=(0<<16); // no fog
blend|=(nv04->blend->b_enable<<20);
blend|=(nv04_blend_func(nv04->blend->b_src)<<24);
blend|=(nv04_blend_func(nv04->blend->b_dst)<<28);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_BLEND, 1);
OUT_RING(chan, blend);
}
static void nv04_emit_sampler(struct nv04_context *nv04, int unit)
{
struct nv04_miptree *nv04mt = nv04->tex_miptree[unit];
struct pipe_texture *pt = &nv04mt->base;
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
struct nouveau_bo *bo = nouveau_bo(nv04mt->buffer);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_OFFSET, 3);
OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RELOCd(chan, bo, (nv04->fragtex.format | nv04->sampler[unit]->format), NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/);
OUT_RING(chan, nv04->sampler[unit]->filter);
}
static void nv04_state_emit_framebuffer(struct nv04_context* nv04)
{
struct pipe_framebuffer_state* fb = nv04->framebuffer;
struct nv04_surface *rt, *zeta;
uint32_t rt_format, w, h;
int colour_format = 0, zeta_format = 0;
struct nv04_miptree *nv04mt = 0;
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *context_surfaces_3d = screen->context_surfaces_3d;
struct nouveau_bo *bo;
w = fb->cbufs[0]->width;
h = fb->cbufs[0]->height;
colour_format = fb->cbufs[0]->format;
rt = (struct nv04_surface *)fb->cbufs[0];
if (fb->zsbuf) {
if (colour_format) {
assert(w == fb->zsbuf->width);
assert(h == fb->zsbuf->height);
} else {
w = fb->zsbuf->width;
h = fb->zsbuf->height;
}
zeta_format = fb->zsbuf->format;
zeta = (struct nv04_surface *)fb->zsbuf;
}
switch (colour_format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case 0:
rt_format = 0x108;
break;
case PIPE_FORMAT_R5G6B5_UNORM:
rt_format = 0x103;
break;
default:
assert(0);
}
BEGIN_RING(chan, context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_FORMAT, 1);
OUT_RING(chan, rt_format);
nv04mt = (struct nv04_miptree *)rt->base.texture;
bo = nouveau_bo(nv04mt->buffer);
/* FIXME pitches have to be aligned ! */
BEGIN_RING(chan, context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_PITCH, 2);
OUT_RING(chan, rt->pitch|(zeta->pitch<<16));
OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
if (fb->zsbuf) {
nv04mt = (struct nv04_miptree *)zeta->base.texture;
BEGIN_RING(chan, context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA, 1);
OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
}
}
void
nv04_emit_hw_state(struct nv04_context *nv04)
{
struct nv04_screen *screen = nv04->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *fahrenheit = screen->fahrenheit;
struct nouveau_grobj *context_surfaces_3d = screen->context_surfaces_3d;
int i;
if (nv04->dirty & NV04_NEW_VERTPROG) {
//nv04_vertprog_bind(nv04, nv04->vertprog.current);
nv04->dirty &= ~NV04_NEW_VERTPROG;
}
if (nv04->dirty & NV04_NEW_FRAGPROG) {
nv04_fragprog_bind(nv04, nv04->fragprog.current);
nv04->dirty &= ~NV04_NEW_FRAGPROG;
nv04->dirty_samplers |= (1<<10);
nv04->dirty_samplers = 0;
}
if (nv04->dirty & NV04_NEW_CONTROL) {
nv04->dirty &= ~NV04_NEW_CONTROL;
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_CONTROL, 1);
OUT_RING(chan, nv04->dsa->control);
}
if (nv04->dirty & NV04_NEW_BLEND) {
nv04->dirty &= ~NV04_NEW_BLEND;
nv04_emit_blend(nv04);
}
if (nv04->dirty & NV04_NEW_VTXARRAYS) {
nv04->dirty &= ~NV04_NEW_VTXARRAYS;
nv04_vertex_layout(nv04);
}
if (nv04->dirty & NV04_NEW_SAMPLER) {
nv04->dirty &= ~NV04_NEW_SAMPLER;
nv04_emit_sampler(nv04, 0);
}
if (nv04->dirty & NV04_NEW_VIEWPORT) {
nv04->dirty &= ~NV04_NEW_VIEWPORT;
// nv04_state_emit_viewport(nv04);
}
if (nv04->dirty & NV04_NEW_FRAMEBUFFER) {
nv04->dirty &= ~NV04_NEW_FRAMEBUFFER;
nv04_state_emit_framebuffer(nv04);
}
/* Emit relocs for every referenced buffer.
* This is to ensure the bufmgr has an accurate idea of how
* the buffer is used. This isn't very efficient, but we don't
* seem to take a significant performance hit. Will be improved
* at some point. Vertex arrays are emitted by nv04_vbo.c
*/
/* Render target */
unsigned rt_pitch = ((struct nv04_surface *)nv04->rt)->pitch;
unsigned zeta_pitch = ((struct nv04_surface *)nv04->zeta)->pitch;
BEGIN_RING(chan, context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_PITCH, 2);
OUT_RING(chan, rt_pitch|(zeta_pitch<<16));
OUT_RELOCl(chan, nouveau_bo(nv04->rt), 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
if (nv04->zeta) {
BEGIN_RING(chan, context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA, 1);
OUT_RELOCl(chan, nouveau_bo(nv04->zeta), 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
}
/* Texture images */
for (i = 0; i < 1; i++) {
if (!(nv04->fp_samplers & (1 << i)))
continue;
struct nv04_miptree *nv04mt = nv04->tex_miptree[i];
struct nouveau_bo *bo = nouveau_bo(nv04mt->buffer);
BEGIN_RING(chan, fahrenheit, NV04_TEXTURED_TRIANGLE_OFFSET, 2);
OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RELOCd(chan, bo, (nv04->fragtex.format | nv04->sampler[i]->format), NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/);
}
}
src/gallium/drivers/nv04/nv04_surface.c
-63
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@@ -1,63 +0,0 @@
/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#include "nv04_context.h"
#include "pipe/p_defines.h"
#include "util/u_simple_screen.h"
#include "util/u_inlines.h"
#include "util/u_tile.h"
static void
nv04_surface_copy(struct pipe_context *pipe,
struct pipe_surface *dest, unsigned destx, unsigned desty,
struct pipe_surface *src, unsigned srcx, unsigned srcy,
unsigned width, unsigned height)
{
struct nv04_context *nv04 = nv04_context(pipe);
struct nv04_surface_2d *eng2d = nv04->screen->eng2d;
eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
nv04_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned destx, unsigned desty, unsigned width,
unsigned height, unsigned value)
{
struct nv04_context *nv04 = nv04_context(pipe);
struct nv04_surface_2d *eng2d = nv04->screen->eng2d;
eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
nv04_init_surface_functions(struct nv04_context *nv04)
{
nv04->pipe.surface_copy = nv04_surface_copy;
nv04->pipe.surface_fill = nv04_surface_fill;
}
src/gallium/drivers/nv04/nv04_transfer.c
-178
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@@ -1,178 +0,0 @@
#include <pipe/p_state.h>
#include <pipe/p_defines.h>
#include <util/u_inlines.h>
#include <util/u_format.h>
#include <util/u_memory.h>
#include <util/u_math.h>
#include <nouveau/nouveau_winsys.h>
#include "nv04_context.h"
#include "nv04_screen.h"
#include "nv04_state.h"
struct nv04_transfer {
struct pipe_transfer base;
struct pipe_surface *surface;
boolean direct;
};
static void
nv04_compatible_transfer_tex(struct pipe_texture *pt, unsigned width, unsigned height,
struct pipe_texture *template)
{
memset(template, 0, sizeof(struct pipe_texture));
template->target = pt->target;
template->format = pt->format;
template->width0 = width;
template->height0 = height;
template->depth0 = 1;
template->last_level = 0;
template->nr_samples = pt->nr_samples;
template->tex_usage = PIPE_TEXTURE_USAGE_DYNAMIC |
NOUVEAU_TEXTURE_USAGE_LINEAR;
}
static struct pipe_transfer *
nv04_transfer_new(struct pipe_screen *pscreen, struct pipe_texture *pt,
unsigned face, unsigned level, unsigned zslice,
enum pipe_transfer_usage usage,
unsigned x, unsigned y, unsigned w, unsigned h)
{
struct nv04_miptree *mt = (struct nv04_miptree *)pt;
struct nv04_transfer *tx;
struct pipe_texture tx_tex_template, *tx_tex;
tx = CALLOC_STRUCT(nv04_transfer);
if (!tx)
return NULL;
pipe_texture_reference(&tx->base.texture, pt);
tx->base.x = x;
tx->base.y = y;
tx->base.width = w;
tx->base.height = h;
tx->base.stride = mt->level[level].pitch;
tx->base.usage = usage;
tx->base.face = face;
tx->base.level = level;
tx->base.zslice = zslice;
/* Direct access to texture */
if ((pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC ||
debug_get_bool_option("NOUVEAU_NO_TRANSFER", TRUE/*XXX:FALSE*/)) &&
pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)
{
tx->direct = true;
tx->surface = pscreen->get_tex_surface(pscreen, pt,
0, 0, 0,
pipe_transfer_buffer_flags(&tx->base));
return &tx->base;
}
tx->direct = false;
nv04_compatible_transfer_tex(pt, w, h, &tx_tex_template);
tx_tex = pscreen->texture_create(pscreen, &tx_tex_template);
if (!tx_tex)
{
FREE(tx);
return NULL;
}
tx->base.stride = ((struct nv04_miptree*)tx_tex)->level[0].pitch;
tx->surface = pscreen->get_tex_surface(pscreen, tx_tex,
face, level, zslice,
pipe_transfer_buffer_flags(&tx->base));
pipe_texture_reference(&tx_tex, NULL);
if (!tx->surface)
{
pipe_surface_reference(&tx->surface, NULL);
FREE(tx);
return NULL;
}
if (usage & PIPE_TRANSFER_READ) {
struct nv04_screen *nvscreen = nv04_screen(pscreen);
struct pipe_surface *src;
src = pscreen->get_tex_surface(pscreen, pt,
face, level, zslice,
PIPE_BUFFER_USAGE_GPU_READ);
/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
/* TODO: Check if SIFM can un-swizzle */
nvscreen->eng2d->copy(nvscreen->eng2d,
tx->surface, 0, 0,
src, x, y,
w, h);
pipe_surface_reference(&src, NULL);
}
return &tx->base;
}
static void
nv04_transfer_del(struct pipe_transfer *ptx)
{
struct nv04_transfer *tx = (struct nv04_transfer *)ptx;
if (!tx->direct && (ptx->usage & PIPE_TRANSFER_WRITE)) {
struct pipe_screen *pscreen = ptx->texture->screen;
struct nv04_screen *nvscreen = nv04_screen(pscreen);
struct pipe_surface *dst;
dst = pscreen->get_tex_surface(pscreen, ptx->texture,
ptx->face, ptx->level, ptx->zslice,
PIPE_BUFFER_USAGE_GPU_WRITE);
/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
nvscreen->eng2d->copy(nvscreen->eng2d,
dst, tx->base.x, tx->base.y,
tx->surface, 0, 0,
tx->base.width, tx->base.height);
pipe_surface_reference(&dst, NULL);
}
pipe_surface_reference(&tx->surface, NULL);
pipe_texture_reference(&ptx->texture, NULL);
FREE(ptx);
}
static void *
nv04_transfer_map(struct pipe_screen *pscreen, struct pipe_transfer *ptx)
{
struct nv04_transfer *tx = (struct nv04_transfer *)ptx;
struct nv04_surface *ns = (struct nv04_surface *)tx->surface;
struct nv04_miptree *mt = (struct nv04_miptree *)tx->surface->texture;
void *map = pipe_buffer_map(pscreen, mt->buffer,
pipe_transfer_buffer_flags(ptx));
if(!tx->direct)
return map + ns->base.offset;
else
return map + ns->base.offset + ptx->y * ns->pitch + ptx->x * util_format_get_blocksize(ptx->texture->format);
}
static void
nv04_transfer_unmap(struct pipe_screen *pscreen, struct pipe_transfer *ptx)
{
struct nv04_transfer *tx = (struct nv04_transfer *)ptx;
struct nv04_miptree *mt = (struct nv04_miptree *)tx->surface->texture;
pipe_buffer_unmap(pscreen, mt->buffer);
}
void
nv04_screen_init_transfer_functions(struct pipe_screen *pscreen)
{
pscreen->get_tex_transfer = nv04_transfer_new;
pscreen->tex_transfer_destroy = nv04_transfer_del;
pscreen->transfer_map = nv04_transfer_map;
pscreen->transfer_unmap = nv04_transfer_unmap;
}
src/gallium/drivers/nv04/nv04_vbo.c
-78
View File
@@ -1,78 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_context.h"
#include "pipe/p_state.h"
#include "util/u_inlines.h"
#include "nv04_context.h"
#include "nv04_state.h"
#include "nouveau/nouveau_channel.h"
#include "nouveau/nouveau_pushbuf.h"
void nv04_draw_elements( struct pipe_context *pipe,
struct pipe_buffer *indexBuffer,
unsigned indexSize,
unsigned prim, unsigned start, unsigned count)
{
struct pipe_screen *pscreen = pipe->screen;
struct nv04_context *nv04 = nv04_context( pipe );
struct draw_context *draw = nv04->draw;
unsigned i;
nv04_emit_hw_state(nv04);
/*
* Map vertex buffers
*/
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (nv04->vtxbuf[i].buffer) {
void *buf
= pipe_buffer_map(pscreen,
nv04->vtxbuf[i].buffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_vertex_buffer(draw, i, buf);
}
}
/* Map index buffer, if present */
if (indexBuffer) {
void *mapped_indexes
= pipe_buffer_map(pscreen, indexBuffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_element_buffer(draw, indexSize, mapped_indexes);
}
else {
/* no index/element buffer */
draw_set_mapped_element_buffer(draw, 0, NULL);
}
draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0,
nv04->constbuf[PIPE_SHADER_VERTEX],
nv04->constbuf_nr[PIPE_SHADER_VERTEX]);
/* draw! */
draw_arrays(nv04->draw, prim, start, count);
/*
* unmap vertex/index buffers
*/
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (nv04->vtxbuf[i].buffer) {
pipe_buffer_unmap(pscreen, nv04->vtxbuf[i].buffer);
draw_set_mapped_vertex_buffer(draw, i, NULL);
}
}
if (indexBuffer) {
pipe_buffer_unmap(pscreen, indexBuffer);
draw_set_mapped_element_buffer(draw, 0, NULL);
}
}
void nv04_draw_arrays( struct pipe_context *pipe,
unsigned prim, unsigned start, unsigned count)
{
printf("coucou in draw arrays\n");
nv04_draw_elements(pipe, NULL, 0, prim, start, count);
}
src/gallium/drivers/nv10/Makefile
-20
View File
@@ -1,20 +0,0 @@
TOP = ../../../..
include $(TOP)/configs/current
LIBNAME = nv10
C_SOURCES = \
nv10_clear.c \
nv10_context.c \
nv10_fragprog.c \
nv10_fragtex.c \
nv10_miptree.c \
nv10_prim_vbuf.c \
nv10_screen.c \
nv10_state.c \
nv10_state_emit.c \
nv10_surface.c \
nv10_transfer.c \
nv10_vbo.c
include ../../Makefile.template
src/gallium/drivers/nv10/nv10_clear.c
-14
View File
@@ -1,14 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "util/u_clear.h"
#include "nv10_context.h"
void
nv10_clear(struct pipe_context *pipe, unsigned buffers,
const float *rgba, double depth, unsigned stencil)
{
util_clear(pipe, nv10_context(pipe)->framebuffer, buffers, rgba, depth,
stencil);
}
src/gallium/drivers/nv10/nv10_context.c
-298
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@@ -1,298 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_defines.h"
#include "util/u_simple_screen.h"
#include "nv10_context.h"
#include "nv10_screen.h"
static void
nv10_flush(struct pipe_context *pipe, unsigned flags,
struct pipe_fence_handle **fence)
{
struct nv10_context *nv10 = nv10_context(pipe);
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
draw_flush(nv10->draw);
FIRE_RING(chan);
if (fence)
*fence = NULL;
}
static void
nv10_destroy(struct pipe_context *pipe)
{
struct nv10_context *nv10 = nv10_context(pipe);
if (nv10->draw)
draw_destroy(nv10->draw);
FREE(nv10);
}
static void nv10_init_hwctx(struct nv10_context *nv10)
{
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
int i;
float projectionmatrix[16];
BEGIN_RING(chan, celsius, NV10TCL_DMA_NOTIFY, 1);
OUT_RING (chan, screen->sync->handle);
BEGIN_RING(chan, celsius, NV10TCL_DMA_IN_MEMORY0, 2);
OUT_RING (chan, chan->vram->handle);
OUT_RING (chan, chan->gart->handle);
BEGIN_RING(chan, celsius, NV10TCL_DMA_IN_MEMORY2, 2);
OUT_RING (chan, chan->vram->handle);
OUT_RING (chan, chan->vram->handle);
BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_RT_HORIZ, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 1);
OUT_RING (chan, (0x7ff<<16)|0x800);
BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_VERT(0), 1);
OUT_RING (chan, (0x7ff<<16)|0x800);
for (i=1;i<8;i++) {
BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(i), 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_VERT(i), 1);
OUT_RING (chan, 0);
}
BEGIN_RING(chan, celsius, 0x290, 1);
OUT_RING (chan, (0x10<<16)|1);
BEGIN_RING(chan, celsius, 0x3f4, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
OUT_RING (chan, 0);
if (nv10->screen->celsius->grclass != NV10TCL) {
/* For nv11, nv17 */
BEGIN_RING(chan, celsius, 0x120, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
OUT_RING (chan, 2);
BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
OUT_RING (chan, 0);
}
BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
OUT_RING (chan, 0);
/* Set state */
BEGIN_RING(chan, celsius, NV10TCL_FOG_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_FUNC, 2);
OUT_RING (chan, 0x207);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(0), 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_RC_IN_ALPHA(0), 12);
OUT_RING (chan, 0x30141010);
OUT_RING (chan, 0);
OUT_RING (chan, 0x20040000);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0x00000c00);
OUT_RING (chan, 0);
OUT_RING (chan, 0x00000c00);
OUT_RING (chan, 0x18000000);
OUT_RING (chan, 0x300e0300);
OUT_RING (chan, 0x0c091c80);
BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_DITHER_ENABLE, 2);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_WEIGHT_ENABLE, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_SRC, 4);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0x8006);
BEGIN_RING(chan, celsius, NV10TCL_STENCIL_MASK, 8);
OUT_RING (chan, 0xff);
OUT_RING (chan, 0x207);
OUT_RING (chan, 0);
OUT_RING (chan, 0xff);
OUT_RING (chan, 0x1e00);
OUT_RING (chan, 0x1e00);
OUT_RING (chan, 0x1e00);
OUT_RING (chan, 0x1d01);
BEGIN_RING(chan, celsius, NV10TCL_NORMALIZE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_FOG_ENABLE, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_LIGHT_MODEL, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_SEPARATE_SPECULAR_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_ENABLED_LIGHTS, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_FUNC, 1);
OUT_RING (chan, 0x201);
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_TEST_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_POLYGON_OFFSET_FACTOR, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_POINT_SIZE, 1);
OUT_RING (chan, 8);
BEGIN_RING(chan, celsius, NV10TCL_POINT_PARAMETERS_ENABLE, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_LINE_WIDTH, 1);
OUT_RING (chan, 8);
BEGIN_RING(chan, celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_POLYGON_MODE_FRONT, 2);
OUT_RING (chan, 0x1b02);
OUT_RING (chan, 0x1b02);
BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE, 2);
OUT_RING (chan, 0x405);
OUT_RING (chan, 0x901);
BEGIN_RING(chan, celsius, NV10TCL_POLYGON_SMOOTH_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_TX_GEN_S(0), 8);
for (i=0;i<8;i++) {
OUT_RING (chan, 0);
}
BEGIN_RING(chan, celsius, NV10TCL_FOG_EQUATION_CONSTANT, 3);
OUT_RING (chan, 0x3fc00000); /* -1.50 */
OUT_RING (chan, 0xbdb8aa0a); /* -0.09 */
OUT_RING (chan, 0); /* 0.00 */
BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_FOG_MODE, 2);
OUT_RING (chan, 0x802);
OUT_RING (chan, 2);
/* for some reason VIEW_MATRIX_ENABLE need to be 6 instead of 4 when
* using texturing, except when using the texture matrix
*/
BEGIN_RING(chan, celsius, NV10TCL_VIEW_MATRIX_ENABLE, 1);
OUT_RING (chan, 6);
BEGIN_RING(chan, celsius, NV10TCL_COLOR_MASK, 1);
OUT_RING (chan, 0x01010101);
/* Set vertex component */
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_COL_4F_R, 4);
OUT_RINGf (chan, 1.0);
OUT_RINGf (chan, 1.0);
OUT_RINGf (chan, 1.0);
OUT_RINGf (chan, 1.0);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_COL2_3F_R, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_NOR_3F_X, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RINGf (chan, 1.0);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_TX0_4F_S, 4);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 1.0);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_TX1_4F_S, 4);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 1.0);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_FOG_1F, 1);
OUT_RINGf (chan, 0.0);
BEGIN_RING(chan, celsius, NV10TCL_EDGEFLAG_ENABLE, 1);
OUT_RING (chan, 1);
memset(projectionmatrix, 0, sizeof(projectionmatrix));
BEGIN_RING(chan, celsius, NV10TCL_PROJECTION_MATRIX(0), 16);
projectionmatrix[0*4+0] = 1.0;
projectionmatrix[1*4+1] = 1.0;
projectionmatrix[2*4+2] = 1.0;
projectionmatrix[3*4+3] = 1.0;
for (i=0;i<16;i++) {
OUT_RINGf (chan, projectionmatrix[i]);
}
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_RANGE_NEAR, 2);
OUT_RING (chan, 0.0);
OUT_RINGf (chan, 16777216.0);
BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_TRANSLATE_X, 4);
OUT_RINGf (chan, -2048.0);
OUT_RINGf (chan, -2048.0);
OUT_RINGf (chan, 16777215.0 * 0.5);
OUT_RING (chan, 0);
FIRE_RING (chan);
}
struct pipe_context *
nv10_create(struct pipe_screen *pscreen, unsigned pctx_id)
{
struct nv10_screen *screen = nv10_screen(pscreen);
struct pipe_winsys *ws = pscreen->winsys;
struct nv10_context *nv10;
struct nouveau_winsys *nvws = screen->nvws;
nv10 = CALLOC(1, sizeof(struct nv10_context));
if (!nv10)
return NULL;
nv10->screen = screen;
nv10->pctx_id = pctx_id;
nv10->nvws = nvws;
nv10->pipe.winsys = ws;
nv10->pipe.screen = pscreen;
nv10->pipe.destroy = nv10_destroy;
nv10->pipe.draw_arrays = nv10_draw_arrays;
nv10->pipe.draw_elements = nv10_draw_elements;
nv10->pipe.clear = nv10_clear;
nv10->pipe.flush = nv10_flush;
nv10->pipe.is_texture_referenced = nouveau_is_texture_referenced;
nv10->pipe.is_buffer_referenced = nouveau_is_buffer_referenced;
nv10_init_surface_functions(nv10);
nv10_init_state_functions(nv10);
nv10->draw = draw_create();
assert(nv10->draw);
draw_set_rasterize_stage(nv10->draw, nv10_draw_vbuf_stage(nv10));
nv10_init_hwctx(nv10);
return &nv10->pipe;
}
src/gallium/drivers/nv10/nv10_context.h
-153
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@@ -1,153 +0,0 @@
#ifndef __NV10_CONTEXT_H__
#define __NV10_CONTEXT_H__
#include <stdio.h>
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_compiler.h"
#include "util/u_memory.h"
#include "util/u_math.h"
#include "draw/draw_vertex.h"
#include "nouveau/nouveau_winsys.h"
#include "nouveau/nouveau_gldefs.h"
#include "nouveau/nouveau_context.h"
#include "nv10_state.h"
#define NOUVEAU_ERR(fmt, args...) \
fprintf(stderr, "%s:%d - "fmt, __func__, __LINE__, ##args);
#define NOUVEAU_MSG(fmt, args...) \
fprintf(stderr, "nouveau: "fmt, ##args);
#define NV10_NEW_VERTPROG (1 << 0)
#define NV10_NEW_FRAGPROG (1 << 1)
#define NV10_NEW_VTXARRAYS (1 << 2)
#define NV10_NEW_BLEND (1 << 3)
#define NV10_NEW_BLENDCOL (1 << 4)
#define NV10_NEW_RAST (1 << 5)
#define NV10_NEW_DSA (1 << 6)
#define NV10_NEW_VIEWPORT (1 << 7)
#define NV10_NEW_SCISSOR (1 << 8)
#define NV10_NEW_FRAMEBUFFER (1 << 9)
#include "nv10_screen.h"
struct nv10_context {
struct pipe_context pipe;
struct nouveau_winsys *nvws;
struct nv10_screen *screen;
unsigned pctx_id;
struct draw_context *draw;
uint32_t dirty;
struct nv10_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
struct nv10_miptree *tex_miptree[PIPE_MAX_SAMPLERS];
unsigned dirty_samplers;
unsigned fp_samplers;
unsigned vp_samplers;
uint32_t rt_enable;
struct pipe_buffer *rt[4];
struct pipe_buffer *zeta;
uint32_t lma_offset;
struct nv10_blend_state *blend;
struct pipe_blend_color *blend_color;
struct nv10_rasterizer_state *rast;
struct nv10_depth_stencil_alpha_state *dsa;
struct pipe_viewport_state *viewport;
struct pipe_scissor_state *scissor;
struct pipe_framebuffer_state *framebuffer;
//struct pipe_buffer *constbuf[PIPE_SHADER_TYPES];
float *constbuf[PIPE_SHADER_TYPES][32][4];
unsigned constbuf_nr[PIPE_SHADER_TYPES];
struct vertex_info vertex_info;
struct {
struct pipe_buffer *buffer;
uint32_t format;
} tex[2];
unsigned vb_enable;
struct {
struct pipe_buffer *buffer;
unsigned delta;
} vb[16];
/* struct {
struct nouveau_resource *exec_heap;
struct nouveau_resource *data_heap;
struct nv10_vertex_program *active;
struct nv10_vertex_program *current;
} vertprog;
*/
struct {
struct nv10_fragment_program *active;
struct nv10_fragment_program *current;
struct pipe_buffer *constant_buf;
} fragprog;
struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
struct pipe_vertex_element vtxelt[PIPE_MAX_ATTRIBS];
};
static INLINE struct nv10_context *
nv10_context(struct pipe_context *pipe)
{
return (struct nv10_context *)pipe;
}
extern void nv10_init_state_functions(struct nv10_context *nv10);
extern void nv10_init_surface_functions(struct nv10_context *nv10);
extern void nv10_screen_init_miptree_functions(struct pipe_screen *pscreen);
/* nv10_clear.c */
extern void nv10_clear(struct pipe_context *pipe, unsigned buffers,
const float *rgba, double depth, unsigned stencil);
/* nv10_draw.c */
extern struct draw_stage *nv10_draw_render_stage(struct nv10_context *nv10);
/* nv10_fragprog.c */
extern void nv10_fragprog_bind(struct nv10_context *,
struct nv10_fragment_program *);
extern void nv10_fragprog_destroy(struct nv10_context *,
struct nv10_fragment_program *);
/* nv10_fragtex.c */
extern void nv10_fragtex_bind(struct nv10_context *);
/* nv10_prim_vbuf.c */
struct draw_stage *nv10_draw_vbuf_stage( struct nv10_context *nv10 );
extern void nv10_vtxbuf_bind(struct nv10_context* nv10);
/* nv10_state.c and friends */
extern void nv10_emit_hw_state(struct nv10_context *nv10);
extern void nv10_state_tex_update(struct nv10_context *nv10);
/* nv10_vbo.c */
extern void nv10_draw_arrays(struct pipe_context *, unsigned mode,
unsigned start, unsigned count);
extern void nv10_draw_elements( struct pipe_context *pipe,
struct pipe_buffer *indexBuffer,
unsigned indexSize,
unsigned prim, unsigned start, unsigned count);
#endif
src/gallium/drivers/nv10/nv10_fragprog.c
-21
View File
@@ -1,21 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_shader_tokens.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_util.h"
#include "nv10_context.h"
void
nv10_fragprog_bind(struct nv10_context *nv10, struct nv10_fragment_program *fp)
{
}
void
nv10_fragprog_destroy(struct nv10_context *nv10,
struct nv10_fragment_program *fp)
{
}
src/gallium/drivers/nv10/nv10_fragtex.c
-130
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@@ -1,130 +0,0 @@
#include "nv10_context.h"
#include "nouveau/nouveau_util.h"
#define _(m,tf) \
{ \
TRUE, \
PIPE_FORMAT_##m, \
NV10TCL_TX_FORMAT_FORMAT_##tf, \
}
struct nv10_texture_format {
boolean defined;
uint pipe;
int format;
};
static struct nv10_texture_format
nv10_texture_formats[] = {
_(A8R8G8B8_UNORM, A8R8G8B8),
_(A1R5G5B5_UNORM, A1R5G5B5),
_(A4R4G4B4_UNORM, A4R4G4B4),
_(L8_UNORM , L8 ),
_(A8_UNORM , A8 ),
_(A8L8_UNORM , A8L8 ),
// _(RGB_DXT1 , DXT1, ),
// _(RGBA_DXT1 , DXT1, ),
// _(RGBA_DXT3 , DXT3, ),
// _(RGBA_DXT5 , DXT5, ),
{},
};
static struct nv10_texture_format *
nv10_fragtex_format(uint pipe_format)
{
struct nv10_texture_format *tf = nv10_texture_formats;
while (tf->defined) {
if (tf->pipe == pipe_format)
return tf;
tf++;
}
return NULL;
}
static void
nv10_fragtex_build(struct nv10_context *nv10, int unit)
{
#if 0
struct nv10_sampler_state *ps = nv10->tex_sampler[unit];
struct nv10_miptree *nv10mt = nv10->tex_miptree[unit];
struct pipe_texture *pt = &nv10mt->base;
struct nv10_texture_format *tf;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
uint32_t txf, txs, txp;
tf = nv10_fragtex_format(pt->format);
if (!tf || !tf->defined) {
NOUVEAU_ERR("Unsupported texture format: 0x%x\n", pt->format);
return;
}
txf = tf->format << 8;
txf |= (pt->last_level + 1) << 16;
txf |= log2i(pt->width0) << 20;
txf |= log2i(pt->height0) << 24;
txf |= log2i(pt->depth0) << 28;
txf |= 8;
switch (pt->target) {
case PIPE_TEXTURE_CUBE:
txf |= NV10TCL_TX_FORMAT_CUBE_MAP;
/* fall-through */
case PIPE_TEXTURE_2D:
txf |= (2<<4);
break;
case PIPE_TEXTURE_1D:
txf |= (1<<4);
break;
default:
NOUVEAU_ERR("Unknown target %d\n", pt->target);
return;
}
BEGIN_RING(chan, celsius, NV10TCL_TX_OFFSET(unit), 8);
OUT_RELOCl(chan, nouveau_bo(nv10mt->buffer), 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RELOCd(chan, nouveau_bo(nv10mt->buffer),txf,NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/);
OUT_RING (chan, ps->wrap);
OUT_RING (chan, 0x40000000); /* enable */
OUT_RING (chan, txs);
OUT_RING (chan, ps->filt | 0x2000 /* magic */);
OUT_RING (chan, (pt->width0 << 16) | pt->height0);
OUT_RING (chan, ps->bcol);
#endif
}
void
nv10_fragtex_bind(struct nv10_context *nv10)
{
#if 0
struct nv10_fragment_program *fp = nv10->fragprog.active;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
unsigned samplers, unit;
samplers = nv10->fp_samplers & ~fp->samplers;
while (samplers) {
unit = ffs(samplers) - 1;
samplers &= ~(1 << unit);
BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(unit), 1);
OUT_RING (chan, 0);
}
samplers = nv10->dirty_samplers & fp->samplers;
while (samplers) {
unit = ffs(samplers) - 1;
samplers &= ~(1 << unit);
nv10_fragtex_build(nv10, unit);
}
nv10->fp_samplers = fp->samplers;
#endif
}
src/gallium/drivers/nv10/nv10_miptree.c
-165
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@@ -1,165 +0,0 @@
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "util/u_inlines.h"
#include "util/u_format.h"
#include "util/u_math.h"
#include "nv10_context.h"
#include "nv10_screen.h"
static void
nv10_miptree_layout(struct nv10_miptree *nv10mt)
{
struct pipe_texture *pt = &nv10mt->base;
boolean swizzled = FALSE;
uint width = pt->width0;
uint offset = 0;
int nr_faces, l, f;
if (pt->target == PIPE_TEXTURE_CUBE) {
nr_faces = 6;
} else {
nr_faces = 1;
}
for (l = 0; l <= pt->last_level; l++) {
if (swizzled)
nv10mt->level[l].pitch = util_format_get_stride(pt->format, width);
else
nv10mt->level[l].pitch = util_format_get_stride(pt->format, pt->width0);
nv10mt->level[l].pitch = (nv10mt->level[l].pitch + 63) & ~63;
nv10mt->level[l].image_offset =
CALLOC(nr_faces, sizeof(unsigned));
width = u_minify(width, 1);
}
for (f = 0; f < nr_faces; f++) {
for (l = 0; l <= pt->last_level; l++) {
nv10mt->level[l].image_offset[f] = offset;
offset += nv10mt->level[l].pitch * u_minify(pt->height0, l);
}
}
nv10mt->total_size = offset;
}
static struct pipe_texture *
nv10_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
const unsigned *stride, struct pipe_buffer *pb)
{
struct nv10_miptree *mt;
/* Only supports 2D, non-mipmapped textures for the moment */
if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
pt->depth0 != 1)
return NULL;
mt = CALLOC_STRUCT(nv10_miptree);
if (!mt)
return NULL;
mt->base = *pt;
pipe_reference_init(&mt->base.reference, 1);
mt->base.screen = pscreen;
mt->level[0].pitch = stride[0];
mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
pipe_buffer_reference(&mt->buffer, pb);
mt->bo = nouveau_bo(mt->buffer);
return &mt->base;
}
static struct pipe_texture *
nv10_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt)
{
struct nv10_miptree *mt;
mt = MALLOC(sizeof(struct nv10_miptree));
if (!mt)
return NULL;
mt->base = *pt;
pipe_reference_init(&mt->base.reference, 1);
mt->base.screen = screen;
nv10_miptree_layout(mt);
mt->buffer = screen->buffer_create(screen, 256, PIPE_BUFFER_USAGE_PIXEL,
mt->total_size);
if (!mt->buffer) {
FREE(mt);
return NULL;
}
mt->bo = nouveau_bo(mt->buffer);
return &mt->base;
}
static void
nv10_miptree_destroy(struct pipe_texture *pt)
{
struct nv10_miptree *nv10mt = (struct nv10_miptree *)pt;
int l;
pipe_buffer_reference(&nv10mt->buffer, NULL);
for (l = 0; l <= pt->last_level; l++) {
if (nv10mt->level[l].image_offset)
FREE(nv10mt->level[l].image_offset);
}
FREE(nv10mt);
}
static void
nv10_miptree_update(struct pipe_context *pipe, struct pipe_texture *mt,
uint face, uint levels)
{
}
static struct pipe_surface *
nv10_miptree_surface_get(struct pipe_screen *screen, struct pipe_texture *pt,
unsigned face, unsigned level, unsigned zslice,
unsigned flags)
{
struct nv10_miptree *nv10mt = (struct nv10_miptree *)pt;
struct nv04_surface *ns;
ns = CALLOC_STRUCT(nv04_surface);
if (!ns)
return NULL;
pipe_texture_reference(&ns->base.texture, pt);
ns->base.format = pt->format;
ns->base.width = u_minify(pt->width0, level);
ns->base.height = u_minify(pt->height0, level);
ns->base.usage = flags;
pipe_reference_init(&ns->base.reference, 1);
ns->base.face = face;
ns->base.level = level;
ns->base.zslice = zslice;
ns->pitch = nv10mt->level[level].pitch;
if (pt->target == PIPE_TEXTURE_CUBE) {
ns->base.offset = nv10mt->level[level].image_offset[face];
} else {
ns->base.offset = nv10mt->level[level].image_offset[0];
}
return &ns->base;
}
static void
nv10_miptree_surface_destroy(struct pipe_surface *surface)
{
}
void nv10_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv10_miptree_create;
pscreen->texture_blanket = nv10_miptree_blanket;
pscreen->texture_destroy = nv10_miptree_destroy;
pscreen->get_tex_surface = nv10_miptree_surface_get;
pscreen->tex_surface_destroy = nv10_miptree_surface_destroy;
}
src/gallium/drivers/nv10/nv10_prim_vbuf.c
-267
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@@ -1,267 +0,0 @@
/**************************************************************************
*
* Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/**
* \file
* Build post-transformation, post-clipping vertex buffers and element
* lists by hooking into the end of the primitive pipeline and
* manipulating the vertex_id field in the vertex headers.
*
* XXX: work in progress
*
* \author José Fonseca <jrfonseca@tungstengraphics.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
#include "util/u_debug.h"
#include "util/u_inlines.h"
#include "nv10_context.h"
#include "nv10_state.h"
#include "draw/draw_vbuf.h"
/**
* Primitive renderer for nv10.
*/
struct nv10_vbuf_render {
struct vbuf_render base;
struct nv10_context *nv10;
/** Vertex buffer */
struct pipe_buffer* buffer;
/** Vertex size in bytes */
unsigned vertex_size;
/** Hardware primitive */
unsigned hwprim;
};
void nv10_vtxbuf_bind( struct nv10_context* nv10 )
{
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
int i;
for(i = 0; i < 8; i++) {
BEGIN_RING(chan, celsius, NV10TCL_VTXBUF_ADDRESS(i), 1);
OUT_RING(chan, 0/*nv10->vtxbuf*/);
BEGIN_RING(chan, celsius, NV10TCL_VTXFMT(i), 1);
OUT_RING(chan, 0/*XXX*/);
}
}
/**
* Basically a cast wrapper.
*/
static INLINE struct nv10_vbuf_render *
nv10_vbuf_render( struct vbuf_render *render )
{
assert(render);
return (struct nv10_vbuf_render *)render;
}
static const struct vertex_info *
nv10_vbuf_render_get_vertex_info( struct vbuf_render *render )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
struct nv10_context *nv10 = nv10_render->nv10;
nv10_emit_hw_state(nv10);
return &nv10->vertex_info;
}
static boolean
nv10_vbuf_render_allocate_vertices( struct vbuf_render *render,
ushort vertex_size,
ushort nr_vertices )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
struct nv10_context *nv10 = nv10_render->nv10;
struct pipe_screen *screen = nv10->pipe.screen;
size_t size = (size_t)vertex_size * (size_t)nr_vertices;
assert(!nv10_render->buffer);
nv10_render->buffer = screen->buffer_create(screen, 64, PIPE_BUFFER_USAGE_VERTEX, size);
nv10->dirty |= NV10_NEW_VTXARRAYS;
if (nv10_render->buffer)
return FALSE;
return TRUE;
}
static void *
nv10_vbuf_render_map_vertices( struct vbuf_render *render )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
struct nv10_context *nv10 = nv10_render->nv10;
struct pipe_screen *pscreen = nv10->pipe.screen;
return pipe_buffer_map(pscreen, nv10_render->buffer,
PIPE_BUFFER_USAGE_CPU_WRITE);
}
static void
nv10_vbuf_render_unmap_vertices( struct vbuf_render *render,
ushort min_index,
ushort max_index )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
struct nv10_context *nv10 = nv10_render->nv10;
struct pipe_screen *pscreen = nv10->pipe.screen;
assert(!nv10_render->buffer);
pipe_buffer_unmap(pscreen, nv10_render->buffer);
}
static boolean
nv10_vbuf_render_set_primitive( struct vbuf_render *render,
unsigned prim )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
unsigned hwp = nvgl_primitive(prim);
if (hwp == 0)
return FALSE;
nv10_render->hwprim = hwp;
return TRUE;
}
static void
nv10_vbuf_render_draw( struct vbuf_render *render,
const ushort *indices,
uint nr_indices)
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
struct nv10_context *nv10 = nv10_render->nv10;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
int push, i;
nv10_emit_hw_state(nv10);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_ARRAY_OFFSET_POS, 1);
OUT_RELOCl(chan, nouveau_bo(nv10_render->buffer), 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);
OUT_RING(chan, nv10_render->hwprim);
if (nr_indices & 1) {
BEGIN_RING(chan, celsius, NV10TCL_VB_ELEMENT_U32, 1);
OUT_RING (chan, indices[0]);
indices++; nr_indices--;
}
while (nr_indices) {
// XXX too big/small ? check the size
push = MIN2(nr_indices, 1200 * 2);
BEGIN_RING_NI(chan, celsius, NV10TCL_VB_ELEMENT_U16, push >> 1);
for (i = 0; i < push; i+=2)
OUT_RING(chan, (indices[i+1] << 16) | indices[i]);
nr_indices -= push;
indices += push;
}
BEGIN_RING(chan, celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);
OUT_RING (chan, 0);
}
static void
nv10_vbuf_render_release_vertices( struct vbuf_render *render )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
assert(nv10_render->buffer);
pipe_buffer_reference(&nv10_render->buffer, NULL);
}
static void
nv10_vbuf_render_destroy( struct vbuf_render *render )
{
struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render);
FREE(nv10_render);
}
/**
* Create a new primitive render.
*/
static struct vbuf_render *
nv10_vbuf_render_create( struct nv10_context *nv10 )
{
struct nv10_vbuf_render *nv10_render = CALLOC_STRUCT(nv10_vbuf_render);
nv10_render->nv10 = nv10;
nv10_render->base.max_vertex_buffer_bytes = 16*1024;
nv10_render->base.max_indices = 1024;
nv10_render->base.get_vertex_info = nv10_vbuf_render_get_vertex_info;
nv10_render->base.allocate_vertices = nv10_vbuf_render_allocate_vertices;
nv10_render->base.map_vertices = nv10_vbuf_render_map_vertices;
nv10_render->base.unmap_vertices = nv10_vbuf_render_unmap_vertices;
nv10_render->base.set_primitive = nv10_vbuf_render_set_primitive;
nv10_render->base.draw = nv10_vbuf_render_draw;
nv10_render->base.release_vertices = nv10_vbuf_render_release_vertices;
nv10_render->base.destroy = nv10_vbuf_render_destroy;
return &nv10_render->base;
}
/**
* Create a new primitive vbuf/render stage.
*/
struct draw_stage *nv10_draw_vbuf_stage( struct nv10_context *nv10 )
{
struct vbuf_render *render;
struct draw_stage *stage;
render = nv10_vbuf_render_create(nv10);
if(!render)
return NULL;
stage = draw_vbuf_stage( nv10->draw, render );
if(!stage) {
render->destroy(render);
return NULL;
}
return stage;
}
src/gallium/drivers/nv10/nv10_screen.c
-208
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@@ -1,208 +0,0 @@
#include "pipe/p_screen.h"
#include "nv10_context.h"
#include "nv10_screen.h"
static int
nv10_screen_get_param(struct pipe_screen *screen, int param)
{
switch (param) {
case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
return 2;
case PIPE_CAP_NPOT_TEXTURES:
return 0;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 0;
case PIPE_CAP_GLSL:
return 0;
case PIPE_CAP_ANISOTROPIC_FILTER:
return 1;
case PIPE_CAP_POINT_SPRITE:
return 0;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 1;
case PIPE_CAP_OCCLUSION_QUERY:
return 0;
case PIPE_CAP_TEXTURE_SHADOW_MAP:
return 0;
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
return 12;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 0;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 12;
case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
return 0;
case PIPE_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
return 0;
case NOUVEAU_CAP_HW_VTXBUF:
case NOUVEAU_CAP_HW_IDXBUF:
return 0;
case PIPE_CAP_INDEP_BLEND_ENABLE:
return 0;
case PIPE_CAP_INDEP_BLEND_FUNC:
return 0;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
return 1;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
}
}
static float
nv10_screen_get_paramf(struct pipe_screen *screen, int param)
{
switch (param) {
case PIPE_CAP_MAX_LINE_WIDTH:
case PIPE_CAP_MAX_LINE_WIDTH_AA:
return 10.0;
case PIPE_CAP_MAX_POINT_WIDTH:
case PIPE_CAP_MAX_POINT_WIDTH_AA:
return 64.0;
case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
return 2.0;
case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
return 4.0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0.0;
}
}
static boolean
nv10_screen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
unsigned tex_usage, unsigned geom_flags)
{
if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
return TRUE;
default:
break;
}
} else
if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
switch (format) {
case PIPE_FORMAT_Z24S8_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z16_UNORM:
return TRUE;
default:
break;
}
} else {
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_A1R5G5B5_UNORM:
case PIPE_FORMAT_A4R4G4B4_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
case PIPE_FORMAT_L8_UNORM:
case PIPE_FORMAT_A8_UNORM:
case PIPE_FORMAT_I8_UNORM:
return TRUE;
default:
break;
}
}
return FALSE;
}
static void
nv10_screen_destroy(struct pipe_screen *pscreen)
{
struct nv10_screen *screen = nv10_screen(pscreen);
nouveau_notifier_free(&screen->sync);
nouveau_grobj_free(&screen->celsius);
nv04_surface_2d_takedown(&screen->eng2d);
nouveau_screen_fini(&screen->base);
FREE(pscreen);
}
static struct pipe_buffer *
nv10_surface_buffer(struct pipe_surface *surf)
{
struct nv10_miptree *mt = (struct nv10_miptree *)surf->texture;
return mt->buffer;
}
struct pipe_screen *
nv10_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
{
struct nv10_screen *screen = CALLOC_STRUCT(nv10_screen);
struct nouveau_channel *chan;
struct pipe_screen *pscreen;
unsigned celsius_class;
int ret;
if (!screen)
return NULL;
pscreen = &screen->base.base;
ret = nouveau_screen_init(&screen->base, dev);
if (ret) {
nv10_screen_destroy(pscreen);
return NULL;
}
chan = screen->base.channel;
pscreen->winsys = ws;
pscreen->destroy = nv10_screen_destroy;
pscreen->get_param = nv10_screen_get_param;
pscreen->get_paramf = nv10_screen_get_paramf;
pscreen->is_format_supported = nv10_screen_is_format_supported;
nv10_screen_init_miptree_functions(pscreen);
nv10_screen_init_transfer_functions(pscreen);
/* 3D object */
if (dev->chipset >= 0x20)
celsius_class = NV11TCL;
else if (dev->chipset >= 0x17)
celsius_class = NV17TCL;
else if (dev->chipset >= 0x11)
celsius_class = NV11TCL;
else
celsius_class = NV10TCL;
if (!celsius_class) {
NOUVEAU_ERR("Unknown nv1x chipset: nv%02x\n", dev->chipset);
return NULL;
}
ret = nouveau_grobj_alloc(chan, 0xbeef0001, celsius_class,
&screen->celsius);
if (ret) {
NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
return FALSE;
}
/* 2D engine setup */
screen->eng2d = nv04_surface_2d_init(&screen->base);
screen->eng2d->buf = nv10_surface_buffer;
/* Notifier for sync purposes */
ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
if (ret) {
NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
nv10_screen_destroy(pscreen);
return NULL;
}
return pscreen;
}
src/gallium/drivers/nv10/nv10_screen.h
-28
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@@ -1,28 +0,0 @@
#ifndef __NV10_SCREEN_H__
#define __NV10_SCREEN_H__
#include "nouveau/nouveau_screen.h"
#include "nv04/nv04_surface_2d.h"
struct nv10_screen {
struct nouveau_screen base;
struct nouveau_winsys *nvws;
/* HW graphics objects */
struct nv04_surface_2d *eng2d;
struct nouveau_grobj *celsius;
struct nouveau_notifier *sync;
};
static INLINE struct nv10_screen *
nv10_screen(struct pipe_screen *screen)
{
return (struct nv10_screen *)screen;
}
void
nv10_screen_init_transfer_functions(struct pipe_screen *pscreen);
#endif
src/gallium/drivers/nv10/nv10_state.c
-590
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@@ -1,590 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "pipe/p_shader_tokens.h"
#include "util/u_inlines.h"
#include "tgsi/tgsi_parse.h"
#include "nv10_context.h"
#include "nv10_state.h"
static void *
nv10_blend_state_create(struct pipe_context *pipe,
const struct pipe_blend_state *cso)
{
struct nv10_blend_state *cb;
cb = MALLOC(sizeof(struct nv10_blend_state));
cb->b_enable = cso->rt[0].blend_enable ? 1 : 0;
cb->b_srcfunc = ((nvgl_blend_func(cso->rt[0].alpha_src_factor)<<16) |
(nvgl_blend_func(cso->rt[0].rgb_src_factor)));
cb->b_dstfunc = ((nvgl_blend_func(cso->rt[0].alpha_dst_factor)<<16) |
(nvgl_blend_func(cso->rt[0].rgb_dst_factor)));
cb->c_mask = (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01<<24) : 0) |
((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01<<16) : 0) |
((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) |
((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01<< 0) : 0));
cb->d_enable = cso->dither ? 1 : 0;
return (void *)cb;
}
static void
nv10_blend_state_bind(struct pipe_context *pipe, void *blend)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->blend = (struct nv10_blend_state*)blend;
nv10->dirty |= NV10_NEW_BLEND;
}
static void
nv10_blend_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static INLINE unsigned
wrap_mode(unsigned wrap) {
unsigned ret;
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
ret = NV10TCL_TX_FORMAT_WRAP_S_REPEAT;
break;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
ret = NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT;
break;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_CLAMP:
ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP:
default:
NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
ret = NV10TCL_TX_FORMAT_WRAP_S_REPEAT;
break;
}
return ret >> NV10TCL_TX_FORMAT_WRAP_S_SHIFT;
}
static void *
nv10_sampler_state_create(struct pipe_context *pipe,
const struct pipe_sampler_state *cso)
{
struct nv10_sampler_state *ps;
uint32_t filter = 0;
ps = MALLOC(sizeof(struct nv10_sampler_state));
ps->wrap = ((wrap_mode(cso->wrap_s) << NV10TCL_TX_FORMAT_WRAP_S_SHIFT) |
(wrap_mode(cso->wrap_t) << NV10TCL_TX_FORMAT_WRAP_T_SHIFT));
ps->en = 0;
if (cso->max_anisotropy > 1.0) {
/* no idea, binary driver sets it, works without it.. meh.. */
ps->wrap |= (1 << 5);
/* if (cso->max_anisotropy >= 16.0) {
ps->en |= NV10TCL_TX_ENABLE_ANISO_16X;
} else
if (cso->max_anisotropy >= 12.0) {
ps->en |= NV10TCL_TX_ENABLE_ANISO_12X;
} else
if (cso->max_anisotropy >= 10.0) {
ps->en |= NV10TCL_TX_ENABLE_ANISO_10X;
} else
if (cso->max_anisotropy >= 8.0) {
ps->en |= NV10TCL_TX_ENABLE_ANISO_8X;
} else
if (cso->max_anisotropy >= 6.0) {
ps->en |= NV10TCL_TX_ENABLE_ANISO_6X;
} else
if (cso->max_anisotropy >= 4.0) {
ps->en |= NV10TCL_TX_ENABLE_ANISO_4X;
} else {
ps->en |= NV10TCL_TX_ENABLE_ANISO_2X;
}*/
}
switch (cso->mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
filter |= NV10TCL_TX_FILTER_MAGNIFY_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
filter |= NV10TCL_TX_FILTER_MAGNIFY_NEAREST;
break;
}
switch (cso->min_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR;
break;
}
break;
case PIPE_TEX_FILTER_NEAREST:
default:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST;
break;
}
break;
}
ps->filt = filter;
/* if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
switch (cso->compare_func) {
case PIPE_FUNC_NEVER:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_NEVER;
break;
case PIPE_FUNC_GREATER:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_GREATER;
break;
case PIPE_FUNC_EQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_EQUAL;
break;
case PIPE_FUNC_GEQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_GEQUAL;
break;
case PIPE_FUNC_LESS:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_LESS;
break;
case PIPE_FUNC_NOTEQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_NOTEQUAL;
break;
case PIPE_FUNC_LEQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_LEQUAL;
break;
case PIPE_FUNC_ALWAYS:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_ALWAYS;
break;
default:
break;
}
}*/
ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
(float_to_ubyte(cso->border_color[0]) << 16) |
(float_to_ubyte(cso->border_color[1]) << 8) |
(float_to_ubyte(cso->border_color[2]) << 0));
return (void *)ps;
}
static void
nv10_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
{
struct nv10_context *nv10 = nv10_context(pipe);
unsigned unit;
for (unit = 0; unit < nr; unit++) {
nv10->tex_sampler[unit] = sampler[unit];
nv10->dirty_samplers |= (1 << unit);
}
}
static void
nv10_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static void
nv10_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
struct pipe_texture **miptree)
{
struct nv10_context *nv10 = nv10_context(pipe);
unsigned unit;
for (unit = 0; unit < nr; unit++) {
nv10->tex_miptree[unit] = (struct nv10_miptree *)miptree[unit];
nv10->dirty_samplers |= (1 << unit);
}
}
static void *
nv10_rasterizer_state_create(struct pipe_context *pipe,
const struct pipe_rasterizer_state *cso)
{
struct nv10_rasterizer_state *rs;
int i;
/*XXX: ignored:
* light_twoside
* offset_cw/ccw -nohw
* scissor
* point_smooth -nohw
* multisample
* offset_units / offset_scale
*/
rs = MALLOC(sizeof(struct nv10_rasterizer_state));
rs->templ = cso;
rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01;
rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff;
rs->line_smooth_en = cso->line_smooth ? 1 : 0;
rs->point_size = *(uint32_t*)&cso->point_size;
rs->poly_smooth_en = cso->poly_smooth ? 1 : 0;
if (cso->front_winding == PIPE_WINDING_CCW) {
rs->front_face = NV10TCL_FRONT_FACE_CCW;
rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw);
rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw);
} else {
rs->front_face = NV10TCL_FRONT_FACE_CW;
rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw);
rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw);
}
switch (cso->cull_mode) {
case PIPE_WINDING_CCW:
rs->cull_face_en = 1;
if (cso->front_winding == PIPE_WINDING_CCW)
rs->cull_face = NV10TCL_CULL_FACE_FRONT;
else
rs->cull_face = NV10TCL_CULL_FACE_BACK;
break;
case PIPE_WINDING_CW:
rs->cull_face_en = 1;
if (cso->front_winding == PIPE_WINDING_CW)
rs->cull_face = NV10TCL_CULL_FACE_FRONT;
else
rs->cull_face = NV10TCL_CULL_FACE_BACK;
break;
case PIPE_WINDING_BOTH:
rs->cull_face_en = 1;
rs->cull_face = NV10TCL_CULL_FACE_FRONT_AND_BACK;
break;
case PIPE_WINDING_NONE:
default:
rs->cull_face_en = 0;
rs->cull_face = 0;
break;
}
if (cso->point_sprite) {
rs->point_sprite = (1 << 0);
for (i = 0; i < 8; i++) {
if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE)
rs->point_sprite |= (1 << (8 + i));
}
} else {
rs->point_sprite = 0;
}
return (void *)rs;
}
static void
nv10_rasterizer_state_bind(struct pipe_context *pipe, void *rast)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->rast = (struct nv10_rasterizer_state*)rast;
draw_set_rasterizer_state(nv10->draw, (nv10->rast ? nv10->rast->templ : NULL));
nv10->dirty |= NV10_NEW_RAST;
}
static void
nv10_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static void *
nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe,
const struct pipe_depth_stencil_alpha_state *cso)
{
struct nv10_depth_stencil_alpha_state *hw;
hw = MALLOC(sizeof(struct nv10_depth_stencil_alpha_state));
hw->depth.func = nvgl_comparison_op(cso->depth.func);
hw->depth.write_enable = cso->depth.writemask ? 1 : 0;
hw->depth.test_enable = cso->depth.enabled ? 1 : 0;
hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0;
hw->stencil.wmask = cso->stencil[0].writemask;
hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func);
hw->stencil.ref = cso->stencil[0].ref_value;
hw->stencil.vmask = cso->stencil[0].valuemask;
hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op);
hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op);
hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op);
hw->alpha.enabled = cso->alpha.enabled ? 1 : 0;
hw->alpha.func = nvgl_comparison_op(cso->alpha.func);
hw->alpha.ref = float_to_ubyte(cso->alpha.ref_value);
return (void *)hw;
}
static void
nv10_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *dsa)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->dsa = (struct nv10_depth_stencil_alpha_state*)dsa;
nv10->dirty |= NV10_NEW_DSA;
}
static void
nv10_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static void *
nv10_vp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *templ)
{
struct nv10_context *nv10 = nv10_context(pipe);
return draw_create_vertex_shader(nv10->draw, templ);
}
static void
nv10_vp_state_bind(struct pipe_context *pipe, void *shader)
{
struct nv10_context *nv10 = nv10_context(pipe);
draw_bind_vertex_shader(nv10->draw, (struct draw_vertex_shader *) shader);
nv10->dirty |= NV10_NEW_VERTPROG;
}
static void
nv10_vp_state_delete(struct pipe_context *pipe, void *shader)
{
struct nv10_context *nv10 = nv10_context(pipe);
draw_delete_vertex_shader(nv10->draw, (struct draw_vertex_shader *) shader);
}
static void *
nv10_fp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
struct nv10_fragment_program *fp;
fp = CALLOC(1, sizeof(struct nv10_fragment_program));
fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
tgsi_scan_shader(cso->tokens, &fp->info);
return (void *)fp;
}
static void
nv10_fp_state_bind(struct pipe_context *pipe, void *hwcso)
{
struct nv10_context *nv10 = nv10_context(pipe);
struct nv10_fragment_program *fp = hwcso;
nv10->fragprog.current = fp;
nv10->dirty |= NV10_NEW_FRAGPROG;
}
static void
nv10_fp_state_delete(struct pipe_context *pipe, void *hwcso)
{
struct nv10_context *nv10 = nv10_context(pipe);
struct nv10_fragment_program *fp = hwcso;
nv10_fragprog_destroy(nv10, fp);
FREE((void*)fp->pipe.tokens);
FREE(fp);
}
static void
nv10_set_blend_color(struct pipe_context *pipe,
const struct pipe_blend_color *bcol)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->blend_color = (struct pipe_blend_color*)bcol;
nv10->dirty |= NV10_NEW_BLENDCOL;
}
static void
nv10_set_clip_state(struct pipe_context *pipe,
const struct pipe_clip_state *clip)
{
struct nv10_context *nv10 = nv10_context(pipe);
draw_set_clip_state(nv10->draw, clip);
}
static void
nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
struct pipe_buffer *buf )
{
struct nv10_context *nv10 = nv10_context(pipe);
struct pipe_screen *pscreen = pipe->screen;
assert(shader < PIPE_SHADER_TYPES);
assert(index == 0);
if (buf) {
void *mapped;
if (buf->size &&
(mapped = pipe_buffer_map(pscreen, buf, PIPE_BUFFER_USAGE_CPU_READ)))
{
memcpy(nv10->constbuf[shader], mapped, buf->size);
nv10->constbuf_nr[shader] =
buf->size / (4 * sizeof(float));
pipe_buffer_unmap(pscreen, buf);
}
}
}
static void
nv10_set_framebuffer_state(struct pipe_context *pipe,
const struct pipe_framebuffer_state *fb)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->framebuffer = (struct pipe_framebuffer_state*)fb;
nv10->dirty |= NV10_NEW_FRAMEBUFFER;
}
static void
nv10_set_polygon_stipple(struct pipe_context *pipe,
const struct pipe_poly_stipple *stipple)
{
NOUVEAU_ERR("line stipple hahaha\n");
}
static void
nv10_set_scissor_state(struct pipe_context *pipe,
const struct pipe_scissor_state *s)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->scissor = (struct pipe_scissor_state*)s;
nv10->dirty |= NV10_NEW_SCISSOR;
}
static void
nv10_set_viewport_state(struct pipe_context *pipe,
const struct pipe_viewport_state *vpt)
{
struct nv10_context *nv10 = nv10_context(pipe);
nv10->viewport = (struct pipe_viewport_state*)vpt;
draw_set_viewport_state(nv10->draw, nv10->viewport);
nv10->dirty |= NV10_NEW_VIEWPORT;
}
static void
nv10_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
const struct pipe_vertex_buffer *vb)
{
struct nv10_context *nv10 = nv10_context(pipe);
memcpy(nv10->vtxbuf, vb, sizeof(*vb) * count);
nv10->dirty |= NV10_NEW_VTXARRAYS;
draw_set_vertex_buffers(nv10->draw, count, vb);
}
static void
nv10_set_vertex_elements(struct pipe_context *pipe, unsigned count,
const struct pipe_vertex_element *ve)
{
struct nv10_context *nv10 = nv10_context(pipe);
memcpy(nv10->vtxelt, ve, sizeof(*ve) * count);
nv10->dirty |= NV10_NEW_VTXARRAYS;
draw_set_vertex_elements(nv10->draw, count, ve);
}
void
nv10_init_state_functions(struct nv10_context *nv10)
{
nv10->pipe.create_blend_state = nv10_blend_state_create;
nv10->pipe.bind_blend_state = nv10_blend_state_bind;
nv10->pipe.delete_blend_state = nv10_blend_state_delete;
nv10->pipe.create_sampler_state = nv10_sampler_state_create;
nv10->pipe.bind_fragment_sampler_states = nv10_sampler_state_bind;
nv10->pipe.delete_sampler_state = nv10_sampler_state_delete;
nv10->pipe.set_fragment_sampler_textures = nv10_set_sampler_texture;
nv10->pipe.create_rasterizer_state = nv10_rasterizer_state_create;
nv10->pipe.bind_rasterizer_state = nv10_rasterizer_state_bind;
nv10->pipe.delete_rasterizer_state = nv10_rasterizer_state_delete;
nv10->pipe.create_depth_stencil_alpha_state =
nv10_depth_stencil_alpha_state_create;
nv10->pipe.bind_depth_stencil_alpha_state =
nv10_depth_stencil_alpha_state_bind;
nv10->pipe.delete_depth_stencil_alpha_state =
nv10_depth_stencil_alpha_state_delete;
nv10->pipe.create_vs_state = nv10_vp_state_create;
nv10->pipe.bind_vs_state = nv10_vp_state_bind;
nv10->pipe.delete_vs_state = nv10_vp_state_delete;
nv10->pipe.create_fs_state = nv10_fp_state_create;
nv10->pipe.bind_fs_state = nv10_fp_state_bind;
nv10->pipe.delete_fs_state = nv10_fp_state_delete;
nv10->pipe.set_blend_color = nv10_set_blend_color;
nv10->pipe.set_clip_state = nv10_set_clip_state;
nv10->pipe.set_constant_buffer = nv10_set_constant_buffer;
nv10->pipe.set_framebuffer_state = nv10_set_framebuffer_state;
nv10->pipe.set_polygon_stipple = nv10_set_polygon_stipple;
nv10->pipe.set_scissor_state = nv10_set_scissor_state;
nv10->pipe.set_viewport_state = nv10_set_viewport_state;
nv10->pipe.set_vertex_buffers = nv10_set_vertex_buffers;
nv10->pipe.set_vertex_elements = nv10_set_vertex_elements;
}
src/gallium/drivers/nv10/nv10_state.h
-140
View File
@@ -1,140 +0,0 @@
#ifndef __NV10_STATE_H__
#define __NV10_STATE_H__
#include "pipe/p_state.h"
#include "tgsi/tgsi_scan.h"
struct nv10_blend_state {
uint32_t b_enable;
uint32_t b_srcfunc;
uint32_t b_dstfunc;
uint32_t c_mask;
uint32_t d_enable;
};
struct nv10_sampler_state {
uint32_t wrap;
uint32_t en;
uint32_t filt;
uint32_t bcol;
};
struct nv10_rasterizer_state {
uint32_t shade_model;
uint32_t line_width;
uint32_t line_smooth_en;
uint32_t point_size;
uint32_t poly_smooth_en;
uint32_t poly_mode_front;
uint32_t poly_mode_back;
uint32_t front_face;
uint32_t cull_face;
uint32_t cull_face_en;
uint32_t point_sprite;
const struct pipe_rasterizer_state *templ;
};
struct nv10_vertex_program_exec {
uint32_t data[4];
boolean has_branch_offset;
int const_index;
};
struct nv10_vertex_program_data {
int index; /* immediates == -1 */
float value[4];
};
struct nv10_vertex_program {
const struct pipe_shader_state *pipe;
boolean translated;
struct nv10_vertex_program_exec *insns;
unsigned nr_insns;
struct nv10_vertex_program_data *consts;
unsigned nr_consts;
struct nouveau_resource *exec;
unsigned exec_start;
struct nouveau_resource *data;
unsigned data_start;
unsigned data_start_min;
uint32_t ir;
uint32_t or;
};
struct nv10_fragment_program_data {
unsigned offset;
unsigned index;
};
struct nv10_fragment_program {
struct pipe_shader_state pipe;
struct tgsi_shader_info info;
boolean translated;
boolean on_hw;
unsigned samplers;
uint32_t *insn;
int insn_len;
struct nv10_fragment_program_data *consts;
unsigned nr_consts;
struct pipe_buffer *buffer;
uint32_t fp_control;
uint32_t fp_reg_control;
};
struct nv10_depth_stencil_alpha_state {
struct {
uint32_t func;
uint32_t write_enable;
uint32_t test_enable;
} depth;
struct {
uint32_t enable;
uint32_t wmask;
uint32_t func;
uint32_t ref;
uint32_t vmask;
uint32_t fail;
uint32_t zfail;
uint32_t zpass;
} stencil;
struct {
uint32_t enabled;
uint32_t func;
uint32_t ref;
} alpha;
};
struct nv10_miptree {
struct pipe_texture base;
struct nouveau_bo *bo;
struct pipe_buffer *buffer;
uint total_size;
struct {
uint pitch;
uint *image_offset;
} level[PIPE_MAX_TEXTURE_LEVELS];
};
#endif
src/gallium/drivers/nv10/nv10_state_emit.c
-333
View File
@@ -1,333 +0,0 @@
#include "nv10_context.h"
#include "nv10_state.h"
static void nv10_state_emit_blend(struct nv10_context* nv10)
{
struct nv10_blend_state *b = nv10->blend;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
BEGIN_RING(chan, celsius, NV10TCL_DITHER_ENABLE, 1);
OUT_RING (chan, b->d_enable);
BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_ENABLE, 3);
OUT_RING (chan, b->b_enable);
OUT_RING (chan, b->b_srcfunc);
OUT_RING (chan, b->b_dstfunc);
BEGIN_RING(chan, celsius, NV10TCL_COLOR_MASK, 1);
OUT_RING (chan, b->c_mask);
}
static void nv10_state_emit_blend_color(struct nv10_context* nv10)
{
struct pipe_blend_color *c = nv10->blend_color;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
BEGIN_RING(chan, celsius, NV10TCL_BLEND_COLOR, 1);
OUT_RING (chan,
(float_to_ubyte(c->color[3]) << 24)|
(float_to_ubyte(c->color[0]) << 16)|
(float_to_ubyte(c->color[1]) << 8) |
(float_to_ubyte(c->color[2]) << 0));
}
static void nv10_state_emit_rast(struct nv10_context* nv10)
{
struct nv10_rasterizer_state *r = nv10->rast;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
BEGIN_RING(chan, celsius, NV10TCL_SHADE_MODEL, 2);
OUT_RING (chan, r->shade_model);
OUT_RING (chan, r->line_width);
BEGIN_RING(chan, celsius, NV10TCL_POINT_SIZE, 1);
OUT_RING (chan, r->point_size);
BEGIN_RING(chan, celsius, NV10TCL_POLYGON_MODE_FRONT, 2);
OUT_RING (chan, r->poly_mode_front);
OUT_RING (chan, r->poly_mode_back);
BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE, 2);
OUT_RING (chan, r->cull_face);
OUT_RING (chan, r->front_face);
BEGIN_RING(chan, celsius, NV10TCL_LINE_SMOOTH_ENABLE, 2);
OUT_RING (chan, r->line_smooth_en);
OUT_RING (chan, r->poly_smooth_en);
BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE_ENABLE, 1);
OUT_RING (chan, r->cull_face_en);
}
static void nv10_state_emit_dsa(struct nv10_context* nv10)
{
struct nv10_depth_stencil_alpha_state *d = nv10->dsa;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_FUNC, 1);
OUT_RING (chan, d->depth.func);
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1);
OUT_RING (chan, d->depth.write_enable);
BEGIN_RING(chan, celsius, NV10TCL_DEPTH_TEST_ENABLE, 1);
OUT_RING (chan, d->depth.test_enable);
#if 0
BEGIN_RING(chan, celsius, NV10TCL_STENCIL_ENABLE, 1);
OUT_RING (chan, d->stencil.enable);
BEGIN_RING(chan, celsius, NV10TCL_STENCIL_MASK, 7);
OUT_RINGp (chan, (uint32_t *)&(d->stencil.wmask), 7);
#endif
BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1);
OUT_RING (chan, d->alpha.enabled);
BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_FUNC, 1);
OUT_RING (chan, d->alpha.func);
BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_REF, 1);
OUT_RING (chan, d->alpha.ref);
}
static void nv10_state_emit_viewport(struct nv10_context* nv10)
{
}
static void nv10_state_emit_scissor(struct nv10_context* nv10)
{
// XXX this is so not working
/* struct pipe_scissor_state *s = nv10->scissor;
BEGIN_RING(celsius, NV10TCL_SCISSOR_HORIZ, 2);
OUT_RING (((s->maxx - s->minx) << 16) | s->minx);
OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/
}
static void nv10_state_emit_framebuffer(struct nv10_context* nv10)
{
struct pipe_framebuffer_state* fb = nv10->framebuffer;
struct nv04_surface *rt, *zeta = NULL;
uint32_t rt_format, w, h;
int colour_format = 0, zeta_format = 0;
struct nv10_miptree *nv10mt = 0;
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
w = fb->cbufs[0]->width;
h = fb->cbufs[0]->height;
colour_format = fb->cbufs[0]->format;
rt = (struct nv04_surface *)fb->cbufs[0];
if (fb->zsbuf) {
if (colour_format) {
assert(w == fb->zsbuf->width);
assert(h == fb->zsbuf->height);
} else {
w = fb->zsbuf->width;
h = fb->zsbuf->height;
}
zeta_format = fb->zsbuf->format;
zeta = (struct nv04_surface *)fb->zsbuf;
}
rt_format = NV10TCL_RT_FORMAT_TYPE_LINEAR;
switch (colour_format) {
case PIPE_FORMAT_X8R8G8B8_UNORM:
rt_format |= NV10TCL_RT_FORMAT_COLOR_X8R8G8B8;
break;
case PIPE_FORMAT_A8R8G8B8_UNORM:
case 0:
rt_format |= NV10TCL_RT_FORMAT_COLOR_A8R8G8B8;
break;
case PIPE_FORMAT_R5G6B5_UNORM:
rt_format |= NV10TCL_RT_FORMAT_COLOR_R5G6B5;
break;
default:
assert(0);
}
if (zeta) {
BEGIN_RING(chan, celsius, NV10TCL_RT_PITCH, 1);
OUT_RING (chan, rt->pitch | (zeta->pitch << 16));
} else {
BEGIN_RING(chan, celsius, NV10TCL_RT_PITCH, 1);
OUT_RING (chan, rt->pitch | (rt->pitch << 16));
}
nv10mt = (struct nv10_miptree *)rt->base.texture;
nv10->rt[0] = nv10mt->buffer;
if (zeta_format)
{
nv10mt = (struct nv10_miptree *)zeta->base.texture;
nv10->zeta = nv10mt->buffer;
}
BEGIN_RING(chan, celsius, NV10TCL_RT_HORIZ, 3);
OUT_RING (chan, (w << 16) | 0);
OUT_RING (chan, (h << 16) | 0);
OUT_RING (chan, rt_format);
BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2);
OUT_RING (chan, ((w - 1) << 16) | 0 | 0x08000800);
OUT_RING (chan, ((h - 1) << 16) | 0 | 0x08000800);
}
static void nv10_vertex_layout(struct nv10_context *nv10)
{
struct nv10_fragment_program *fp = nv10->fragprog.current;
uint32_t src = 0;
int i;
struct vertex_info vinfo;
memset(&vinfo, 0, sizeof(vinfo));
for (i = 0; i < fp->info.num_inputs; i++) {
switch (fp->info.input_semantic_name[i]) {
case TGSI_SEMANTIC_POSITION:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR, src++);
break;
case TGSI_SEMANTIC_COLOR:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_LINEAR, src++);
break;
default:
case TGSI_SEMANTIC_GENERIC:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE, src++);
break;
case TGSI_SEMANTIC_FOG:
draw_emit_vertex_attr(&vinfo, EMIT_4F, INTERP_PERSPECTIVE, src++);
break;
}
}
draw_compute_vertex_size(&vinfo);
}
void
nv10_emit_hw_state(struct nv10_context *nv10)
{
struct nv10_screen *screen = nv10->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *celsius = screen->celsius;
struct nouveau_bo *rt_bo;
int i;
if (nv10->dirty & NV10_NEW_VERTPROG) {
//nv10_vertprog_bind(nv10, nv10->vertprog.current);
nv10->dirty &= ~NV10_NEW_VERTPROG;
}
if (nv10->dirty & NV10_NEW_FRAGPROG) {
nv10_fragprog_bind(nv10, nv10->fragprog.current);
/*XXX: clear NV10_NEW_FRAGPROG if no new program uploaded */
nv10->dirty_samplers |= (1<<10);
nv10->dirty_samplers = 0;
}
if (nv10->dirty_samplers || (nv10->dirty & NV10_NEW_FRAGPROG)) {
nv10_fragtex_bind(nv10);
nv10->dirty &= ~NV10_NEW_FRAGPROG;
}
if (nv10->dirty & NV10_NEW_VTXARRAYS) {
nv10->dirty &= ~NV10_NEW_VTXARRAYS;
nv10_vertex_layout(nv10);
nv10_vtxbuf_bind(nv10);
}
if (nv10->dirty & NV10_NEW_BLEND) {
nv10->dirty &= ~NV10_NEW_BLEND;
nv10_state_emit_blend(nv10);
}
if (nv10->dirty & NV10_NEW_BLENDCOL) {
nv10->dirty &= ~NV10_NEW_BLENDCOL;
nv10_state_emit_blend_color(nv10);
}
if (nv10->dirty & NV10_NEW_RAST) {
nv10->dirty &= ~NV10_NEW_RAST;
nv10_state_emit_rast(nv10);
}
if (nv10->dirty & NV10_NEW_DSA) {
nv10->dirty &= ~NV10_NEW_DSA;
nv10_state_emit_dsa(nv10);
}
if (nv10->dirty & NV10_NEW_VIEWPORT) {
nv10->dirty &= ~NV10_NEW_VIEWPORT;
nv10_state_emit_viewport(nv10);
}
if (nv10->dirty & NV10_NEW_SCISSOR) {
nv10->dirty &= ~NV10_NEW_SCISSOR;
nv10_state_emit_scissor(nv10);
}
if (nv10->dirty & NV10_NEW_FRAMEBUFFER) {
nv10->dirty &= ~NV10_NEW_FRAMEBUFFER;
nv10_state_emit_framebuffer(nv10);
}
/* Emit relocs for every referenced buffer.
* This is to ensure the bufmgr has an accurate idea of how
* the buffer is used. This isn't very efficient, but we don't
* seem to take a significant performance hit. Will be improved
* at some point. Vertex arrays are emitted by nv10_vbo.c
*/
/* Render target */
rt_bo = nouveau_bo(nv10->rt[0]);
// XXX figre out who's who for NV10TCL_DMA_* and fill accordingly
// BEGIN_RING(chan, celsius, NV10TCL_DMA_COLOR0, 1);
// OUT_RELOCo(chan, rt_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(chan, celsius, NV10TCL_COLOR_OFFSET, 1);
OUT_RELOCl(chan, rt_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
if (nv10->zeta) {
struct nouveau_bo *zeta_bo = nouveau_bo(nv10->zeta);
// XXX
// BEGIN_RING(chan, celsius, NV10TCL_DMA_ZETA, 1);
// OUT_RELOCo(chan, zeta_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(chan, celsius, NV10TCL_ZETA_OFFSET, 1);
OUT_RELOCl(chan, zeta_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
/* XXX for when we allocate LMA on nv17 */
/* BEGIN_RING(chan, celsius, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1);
OUT_RELOCl(chan, nouveau_bo(nv10->zeta + lma_offset));*/
}
/* Vertex buffer */
BEGIN_RING(chan, celsius, NV10TCL_DMA_VTXBUF0, 1);
OUT_RELOCo(chan, rt_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(chan, celsius, NV10TCL_COLOR_OFFSET, 1);
OUT_RELOCl(chan, rt_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
/* Texture images */
for (i = 0; i < 2; i++) {
if (!(nv10->fp_samplers & (1 << i)))
continue;
struct nouveau_bo *bo = nouveau_bo(nv10->tex[i].buffer);
BEGIN_RING(chan, celsius, NV10TCL_TX_OFFSET(i), 1);
OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM |
NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_RING(chan, celsius, NV10TCL_TX_FORMAT(i), 1);
OUT_RELOCd(chan, bo, nv10->tex[i].format,
NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
NOUVEAU_BO_OR, NV10TCL_TX_FORMAT_DMA0,
NV10TCL_TX_FORMAT_DMA1);
}
}
src/gallium/drivers/nv10/nv10_surface.c
-63
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@@ -1,63 +0,0 @@
/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#include "nv10_context.h"
#include "pipe/p_defines.h"
#include "util/u_simple_screen.h"
#include "util/u_inlines.h"
#include "util/u_tile.h"
static void
nv10_surface_copy(struct pipe_context *pipe,
struct pipe_surface *dest, unsigned destx, unsigned desty,
struct pipe_surface *src, unsigned srcx, unsigned srcy,
unsigned width, unsigned height)
{
struct nv10_context *nv10 = nv10_context(pipe);
struct nv04_surface_2d *eng2d = nv10->screen->eng2d;
eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
nv10_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned destx, unsigned desty, unsigned width,
unsigned height, unsigned value)
{
struct nv10_context *nv10 = nv10_context(pipe);
struct nv04_surface_2d *eng2d = nv10->screen->eng2d;
eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
nv10_init_surface_functions(struct nv10_context *nv10)
{
nv10->pipe.surface_copy = nv10_surface_copy;
nv10->pipe.surface_fill = nv10_surface_fill;
}
src/gallium/drivers/nv10/nv10_transfer.c
-178
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@@ -1,178 +0,0 @@
#include <pipe/p_state.h>
#include <pipe/p_defines.h>
#include <util/u_inlines.h>
#include <util/u_format.h>
#include <util/u_memory.h>
#include <util/u_math.h>
#include <nouveau/nouveau_winsys.h>
#include "nv10_context.h"
#include "nv10_screen.h"
#include "nv10_state.h"
struct nv10_transfer {
struct pipe_transfer base;
struct pipe_surface *surface;
boolean direct;
};
static void
nv10_compatible_transfer_tex(struct pipe_texture *pt, unsigned width, unsigned height,
struct pipe_texture *template)
{
memset(template, 0, sizeof(struct pipe_texture));
template->target = pt->target;
template->format = pt->format;
template->width0 = width;
template->height0 = height;
template->depth0 = 1;
template->last_level = 0;
template->nr_samples = pt->nr_samples;
template->tex_usage = PIPE_TEXTURE_USAGE_DYNAMIC |
NOUVEAU_TEXTURE_USAGE_LINEAR;
}
static struct pipe_transfer *
nv10_transfer_new(struct pipe_screen *pscreen, struct pipe_texture *pt,
unsigned face, unsigned level, unsigned zslice,
enum pipe_transfer_usage usage,
unsigned x, unsigned y, unsigned w, unsigned h)
{
struct nv10_miptree *mt = (struct nv10_miptree *)pt;
struct nv10_transfer *tx;
struct pipe_texture tx_tex_template, *tx_tex;
tx = CALLOC_STRUCT(nv10_transfer);
if (!tx)
return NULL;
pipe_texture_reference(&tx->base.texture, pt);
tx->base.x = x;
tx->base.y = y;
tx->base.width = w;
tx->base.height = h;
tx->base.stride = mt->level[level].pitch;
tx->base.usage = usage;
tx->base.face = face;
tx->base.level = level;
tx->base.zslice = zslice;
/* Direct access to texture */
if ((pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC ||
debug_get_bool_option("NOUVEAU_NO_TRANSFER", TRUE/*XXX:FALSE*/)) &&
pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)
{
tx->direct = true;
tx->surface = pscreen->get_tex_surface(pscreen, pt,
0, 0, 0,
pipe_transfer_buffer_flags(&tx->base));
return &tx->base;
}
tx->direct = false;
nv10_compatible_transfer_tex(pt, w, h, &tx_tex_template);
tx_tex = pscreen->texture_create(pscreen, &tx_tex_template);
if (!tx_tex)
{
FREE(tx);
return NULL;
}
tx->base.stride = ((struct nv10_miptree*)tx_tex)->level[0].pitch;
tx->surface = pscreen->get_tex_surface(pscreen, tx_tex,
face, level, zslice,
pipe_transfer_buffer_flags(&tx->base));
pipe_texture_reference(&tx_tex, NULL);
if (!tx->surface)
{
pipe_surface_reference(&tx->surface, NULL);
FREE(tx);
return NULL;
}
if (usage & PIPE_TRANSFER_READ) {
struct nv10_screen *nvscreen = nv10_screen(pscreen);
struct pipe_surface *src;
src = pscreen->get_tex_surface(pscreen, pt,
face, level, zslice,
PIPE_BUFFER_USAGE_GPU_READ);
/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
/* TODO: Check if SIFM can un-swizzle */
nvscreen->eng2d->copy(nvscreen->eng2d,
tx->surface, 0, 0,
src, x, y,
w, h);
pipe_surface_reference(&src, NULL);
}
return &tx->base;
}
static void
nv10_transfer_del(struct pipe_transfer *ptx)
{
struct nv10_transfer *tx = (struct nv10_transfer *)ptx;
if (!tx->direct && (ptx->usage & PIPE_TRANSFER_WRITE)) {
struct pipe_screen *pscreen = ptx->texture->screen;
struct nv10_screen *nvscreen = nv10_screen(pscreen);
struct pipe_surface *dst;
dst = pscreen->get_tex_surface(pscreen, ptx->texture,
ptx->face, ptx->level, ptx->zslice,
PIPE_BUFFER_USAGE_GPU_WRITE);
/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
nvscreen->eng2d->copy(nvscreen->eng2d,
dst, tx->base.x, tx->base.y,
tx->surface, 0, 0,
tx->base.width, tx->base.height);
pipe_surface_reference(&dst, NULL);
}
pipe_surface_reference(&tx->surface, NULL);
pipe_texture_reference(&ptx->texture, NULL);
FREE(ptx);
}
static void *
nv10_transfer_map(struct pipe_screen *pscreen, struct pipe_transfer *ptx)
{
struct nv10_transfer *tx = (struct nv10_transfer *)ptx;
struct nv04_surface *ns = (struct nv04_surface *)tx->surface;
struct nv10_miptree *mt = (struct nv10_miptree *)tx->surface->texture;
void *map = pipe_buffer_map(pscreen, mt->buffer,
pipe_transfer_buffer_flags(ptx));
if(!tx->direct)
return map + ns->base.offset;
else
return map + ns->base.offset + ptx->y * ns->pitch + ptx->x * util_format_get_blocksize(ptx->texture->format);
}
static void
nv10_transfer_unmap(struct pipe_screen *pscreen, struct pipe_transfer *ptx)
{
struct nv10_transfer *tx = (struct nv10_transfer *)ptx;
struct nv10_miptree *mt = (struct nv10_miptree *)tx->surface->texture;
pipe_buffer_unmap(pscreen, mt->buffer);
}
void
nv10_screen_init_transfer_functions(struct pipe_screen *pscreen)
{
pscreen->get_tex_transfer = nv10_transfer_new;
pscreen->tex_transfer_destroy = nv10_transfer_del;
pscreen->transfer_map = nv10_transfer_map;
pscreen->transfer_unmap = nv10_transfer_unmap;
}
src/gallium/drivers/nv10/nv10_vbo.c
-78
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@@ -1,78 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_context.h"
#include "pipe/p_state.h"
#include "util/u_inlines.h"
#include "nv10_context.h"
#include "nv10_state.h"
#include "nouveau/nouveau_channel.h"
#include "nouveau/nouveau_pushbuf.h"
void nv10_draw_elements( struct pipe_context *pipe,
struct pipe_buffer *indexBuffer,
unsigned indexSize,
unsigned prim, unsigned start, unsigned count)
{
struct nv10_context *nv10 = nv10_context( pipe );
struct draw_context *draw = nv10->draw;
struct pipe_screen *pscreen = pipe->screen;
unsigned i;
nv10_emit_hw_state(nv10);
/*
* Map vertex buffers
*/
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (nv10->vtxbuf[i].buffer) {
void *buf =
pipe_buffer_map(pscreen, nv10->vtxbuf[i].buffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_vertex_buffer(draw, i, buf);
}
}
/* Map index buffer, if present */
if (indexBuffer) {
void *mapped_indexes
= pipe_buffer_map(pscreen, indexBuffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_element_buffer(draw, indexSize, mapped_indexes);
}
else {
/* no index/element buffer */
draw_set_mapped_element_buffer(draw, 0, NULL);
}
draw_set_mapped_constant_buffer(draw,
PIPE_SHADER_VERTEX,
0,
nv10->constbuf[PIPE_SHADER_VERTEX],
nv10->constbuf_nr[PIPE_SHADER_VERTEX]);
/* draw! */
draw_arrays(nv10->draw, prim, start, count);
/*
* unmap vertex/index buffers
*/
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (nv10->vtxbuf[i].buffer) {
pipe_buffer_unmap(pscreen, nv10->vtxbuf[i].buffer);
draw_set_mapped_vertex_buffer(draw, i, NULL);
}
}
if (indexBuffer) {
pipe_buffer_unmap(pscreen, indexBuffer);
draw_set_mapped_element_buffer(draw, 0, NULL);
}
}
void nv10_draw_arrays( struct pipe_context *pipe,
unsigned prim, unsigned start, unsigned count)
{
nv10_draw_elements(pipe, NULL, 0, prim, start, count);
}
src/gallium/drivers/nv20/Makefile
-21
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@@ -1,21 +0,0 @@
TOP = ../../../..
include $(TOP)/configs/current
LIBNAME = nv20
C_SOURCES = \
nv20_clear.c \
nv20_context.c \
nv20_fragprog.c \
nv20_fragtex.c \
nv20_miptree.c \
nv20_prim_vbuf.c \
nv20_screen.c \
nv20_state.c \
nv20_state_emit.c \
nv20_surface.c \
nv20_transfer.c \
nv20_vbo.c
# nv20_vertprog.c
include ../../Makefile.template
src/gallium/drivers/nv20/nv20_clear.c
-14
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@@ -1,14 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "util/u_clear.h"
#include "nv20_context.h"
void
nv20_clear(struct pipe_context *pipe, unsigned buffers,
const float *rgba, double depth, unsigned stencil)
{
util_clear(pipe, nv20_context(pipe)->framebuffer, buffers, rgba, depth,
stencil);
}
src/gallium/drivers/nv20/nv20_context.c
-424
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@@ -1,424 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_defines.h"
#include "util/u_simple_screen.h"
#include "nv20_context.h"
#include "nv20_screen.h"
static void
nv20_flush(struct pipe_context *pipe, unsigned flags,
struct pipe_fence_handle **fence)
{
struct nv20_context *nv20 = nv20_context(pipe);
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
draw_flush(nv20->draw);
FIRE_RING(chan);
if (fence)
*fence = NULL;
}
static void
nv20_destroy(struct pipe_context *pipe)
{
struct nv20_context *nv20 = nv20_context(pipe);
if (nv20->draw)
draw_destroy(nv20->draw);
FREE(nv20);
}
static void nv20_init_hwctx(struct nv20_context *nv20)
{
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
int i;
float projectionmatrix[16];
const boolean is_nv25tcl = (kelvin->grclass == NV25TCL);
BEGIN_RING(chan, kelvin, NV20TCL_DMA_NOTIFY, 1);
OUT_RING (chan, screen->sync->handle);
BEGIN_RING(chan, kelvin, NV20TCL_DMA_TEXTURE0, 2);
OUT_RING (chan, chan->vram->handle);
OUT_RING (chan, chan->gart->handle); /* TEXTURE1 */
BEGIN_RING(chan, kelvin, NV20TCL_DMA_COLOR, 2);
OUT_RING (chan, chan->vram->handle);
OUT_RING (chan, chan->vram->handle); /* ZETA */
BEGIN_RING(chan, kelvin, NV20TCL_DMA_QUERY, 1);
OUT_RING (chan, 0); /* renouveau: beef0351, unique */
BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1);
OUT_RING (chan, (0xfff << 16) | 0x0);
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1);
OUT_RING (chan, (0xfff << 16) | 0x0);
for (i = 1; i < NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE; i++) {
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(i), 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(i), 1);
OUT_RING (chan, 0);
}
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_MODE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, 0x17e0, 3);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 1.0);
if (is_nv25tcl) {
BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
OUT_RING (chan, NV20TCL_TX_RCOMP_LEQUAL | 0xdb0);
} else {
BEGIN_RING(chan, kelvin, 0x1e68, 1);
OUT_RING (chan, 0x4b800000); /* 16777216.000000 */
BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
OUT_RING (chan, NV20TCL_TX_RCOMP_LEQUAL);
}
BEGIN_RING(chan, kelvin, 0x290, 1);
OUT_RING (chan, (0x10 << 16) | 1);
BEGIN_RING(chan, kelvin, 0x9fc, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, 0x1d80, 1);
OUT_RING (chan, 1);
BEGIN_RING(chan, kelvin, 0x9f8, 1);
OUT_RING (chan, 4);
BEGIN_RING(chan, kelvin, 0x17ec, 3);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 1.0);
OUT_RINGf (chan, 0.0);
if (is_nv25tcl) {
BEGIN_RING(chan, kelvin, 0x1d88, 1);
OUT_RING (chan, 3);
BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY9, 1);
OUT_RING (chan, chan->vram->handle);
BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY8, 1);
OUT_RING (chan, chan->vram->handle);
}
BEGIN_RING(chan, kelvin, NV20TCL_DMA_FENCE, 1);
OUT_RING (chan, 0); /* renouveau: beef1e10 */
BEGIN_RING(chan, kelvin, 0x1e98, 1);
OUT_RING (chan, 0);
#if 0
if (is_nv25tcl) {
BEGIN_RING(chan, NvSub3D, NV25TCL_DMA_IN_MEMORY4, 2);
OUT_RING (chan, NvDmaTT); /* renouveau: beef0202 */
OUT_RING (chan, NvDmaFB); /* renouveau: beef0201 */
BEGIN_RING(chan, NvSub3D, NV20TCL_DMA_TEXTURE1, 1);
OUT_RING (chan, NvDmaTT); /* renouveau: beef0202 */
}
#endif
BEGIN_RING(chan, kelvin, NV20TCL_NOTIFY, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, 0x120, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
OUT_RING (chan, 2);
/* error: ILLEGAL_MTHD, PROTECTION_FAULT
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 512.0);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0);
*/
if (is_nv25tcl) {
BEGIN_RING(chan, kelvin, 0x022c, 2);
OUT_RING (chan, 0x280);
OUT_RING (chan, 0x07d28000);
}
/* * illegal method, protection fault
BEGIN_RING(chan, NvSub3D, 0x1c2c, 1);
OUT_RING (chan, 0); */
if (is_nv25tcl) {
BEGIN_RING(chan, kelvin, 0x1da4, 1);
OUT_RING (chan, 0);
}
/* * crashes with illegal method, protection fault
BEGIN_RING(chan, NvSub3D, 0x1c18, 1);
OUT_RING (chan, 0x200); */
BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
OUT_RING (chan, (0 << 16) | 0);
OUT_RING (chan, (0 << 16) | 0);
/* *** Set state *** */
BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_FUNC, 2);
OUT_RING (chan, NV20TCL_ALPHA_FUNC_FUNC_ALWAYS);
OUT_RING (chan, 0); /* NV20TCL_ALPHA_FUNC_REF */
for (i = 0; i < NV20TCL_TX_ENABLE__SIZE; ++i) {
BEGIN_RING(chan, kelvin, NV20TCL_TX_ENABLE(i), 1);
OUT_RING (chan, 0);
}
BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_OP, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_CULL_MODE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_ALPHA(0), 4);
OUT_RING (chan, 0x30d410d0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_RGB(0), 4);
OUT_RING (chan, 0x00000c00);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_RC_ENABLE, 1);
OUT_RING (chan, 0x00011101);
BEGIN_RING(chan, kelvin, NV20TCL_RC_FINAL0, 2);
OUT_RING (chan, 0x130e0300);
OUT_RING (chan, 0x0c091c80);
BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_ALPHA(0), 4);
OUT_RING (chan, 0x00000c00);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_RGB(0), 4);
OUT_RING (chan, 0x20c400c0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_RC_COLOR0, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_RC_CONSTANT_COLOR0(0), 4);
OUT_RING (chan, 0x035125a0);
OUT_RING (chan, 0);
OUT_RING (chan, 0x40002000);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_MULTISAMPLE_CONTROL, 1);
OUT_RING (chan, 0xffff0000);
BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_DITHER_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_SRC, 4);
OUT_RING (chan, NV20TCL_BLEND_FUNC_SRC_ONE);
OUT_RING (chan, NV20TCL_BLEND_FUNC_DST_ZERO);
OUT_RING (chan, 0); /* NV20TCL_BLEND_COLOR */
OUT_RING (chan, NV20TCL_BLEND_EQUATION_FUNC_ADD);
BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_MASK, 7);
OUT_RING (chan, 0xff);
OUT_RING (chan, NV20TCL_STENCIL_FUNC_FUNC_ALWAYS);
OUT_RING (chan, 0); /* NV20TCL_STENCIL_FUNC_REF */
OUT_RING (chan, 0xff); /* NV20TCL_STENCIL_FUNC_MASK */
OUT_RING (chan, NV20TCL_STENCIL_OP_FAIL_KEEP);
OUT_RING (chan, NV20TCL_STENCIL_OP_ZFAIL_KEEP);
OUT_RING (chan, NV20TCL_STENCIL_OP_ZPASS_KEEP);
BEGIN_RING(chan, kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2);
OUT_RING (chan, 0);
OUT_RING (chan, NV20TCL_COLOR_LOGIC_OP_OP_COPY);
BEGIN_RING(chan, kelvin, 0x17cc, 1);
OUT_RING (chan, 0);
if (is_nv25tcl) {
BEGIN_RING(chan, kelvin, 0x1d84, 1);
OUT_RING (chan, 1);
}
BEGIN_RING(chan, kelvin, NV20TCL_LIGHTING_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL, 1);
OUT_RING (chan, 0x00020000);
BEGIN_RING(chan, kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_ENABLED_LIGHTS, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_NORMALIZE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_PATTERN(0),
NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE);
for (i = 0; i < NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE; ++i) {
OUT_RING(chan, 0xffffffff);
}
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 0); /* NV20TCL.POLYGON_OFFSET_LINE_ENABLE */
OUT_RING (chan, 0); /* NV20TCL.POLYGON_OFFSET_FILL_ENABLE */
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_FUNC, 1);
OUT_RING (chan, NV20TCL_DEPTH_FUNC_LESS);
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_FACTOR, 2);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 0.0); /* NV20TCL.POLYGON_OFFSET_UNITS */
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_UNK17D8, 1);
OUT_RING (chan, 1);
if (!is_nv25tcl) {
BEGIN_RING(chan, kelvin, 0x1d84, 1);
OUT_RING (chan, 3);
}
BEGIN_RING(chan, kelvin, NV20TCL_POINT_SIZE, 1);
if (!is_nv25tcl) {
OUT_RING (chan, 8);
} else {
OUT_RINGf (chan, 1.0);
}
if (!is_nv25tcl) {
BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0); /* NV20TCL.POINT_SMOOTH_ENABLE */
} else {
BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, 0x0a1c, 1);
OUT_RING (chan, 0x800);
}
BEGIN_RING(chan, kelvin, NV20TCL_LINE_WIDTH, 1);
OUT_RING (chan, 8);
BEGIN_RING(chan, kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
OUT_RING (chan, NV20TCL_POLYGON_MODE_FRONT_FILL);
OUT_RING (chan, NV20TCL_POLYGON_MODE_BACK_FILL);
BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE, 2);
OUT_RING (chan, NV20TCL_CULL_FACE_BACK);
OUT_RING (chan, NV20TCL_FRONT_FACE_CCW);
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_SMOOTH_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_SHADE_MODEL, 1);
OUT_RING (chan, NV20TCL_SHADE_MODEL_SMOOTH);
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_ENABLE, 1);
OUT_RING (chan, 0);
BEGIN_RING(chan, kelvin, NV20TCL_TX_GEN_S(0), 4 * NV20TCL_TX_GEN_S__SIZE);
for (i=0; i < 4 * NV20TCL_TX_GEN_S__SIZE; ++i) {
OUT_RING(chan, 0);
}
BEGIN_RING(chan, kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3);
OUT_RINGf (chan, 1.5);
OUT_RINGf (chan, -0.090168); /* NV20TCL.FOG_EQUATION_LINEAR */
OUT_RINGf (chan, 0.0); /* NV20TCL.FOG_EQUATION_QUADRATIC */
BEGIN_RING(chan, kelvin, NV20TCL_FOG_MODE, 2);
OUT_RING (chan, NV20TCL_FOG_MODE_EXP_SIGNED);
OUT_RING (chan, NV20TCL_FOG_COORD_FOG);
BEGIN_RING(chan, kelvin, NV20TCL_FOG_ENABLE, 2);
OUT_RING (chan, 0);
OUT_RING (chan, 0); /* NV20TCL.FOG_COLOR */
BEGIN_RING(chan, kelvin, NV20TCL_ENGINE, 1);
OUT_RING (chan, NV20TCL_ENGINE_FIXED);
for (i = 0; i < NV20TCL_TX_MATRIX_ENABLE__SIZE; ++i) {
BEGIN_RING(chan, kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
OUT_RING (chan, 0);
}
BEGIN_RING(chan, kelvin, NV20TCL_VTX_ATTR_4F_X(1), 4 * 15);
OUT_RINGf(chan, 1.0); OUT_RINGf(chan, 0.0); OUT_RINGf(chan, 0.0); OUT_RINGf(chan, 1.0);
OUT_RINGf(chan, 0.0); OUT_RINGf(chan, 0.0); OUT_RINGf(chan, 1.0); OUT_RINGf(chan, 1.0);
OUT_RINGf(chan, 1.0); OUT_RINGf(chan, 1.0); OUT_RINGf(chan, 1.0); OUT_RINGf(chan, 1.0);
for (i = 4; i < 16; ++i) {
OUT_RINGf(chan, 0.0);
OUT_RINGf(chan, 0.0);
OUT_RINGf(chan, 0.0);
OUT_RINGf(chan, 1.0);
}
BEGIN_RING(chan, kelvin, NV20TCL_EDGEFLAG_ENABLE, 1);
OUT_RING (chan, 1);
BEGIN_RING(chan, kelvin, NV20TCL_COLOR_MASK, 1);
OUT_RING (chan, 0x00010101);
BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_VALUE, 1);
OUT_RING (chan, 0);
memset(projectionmatrix, 0, sizeof(projectionmatrix));
projectionmatrix[0*4+0] = 1.0;
projectionmatrix[1*4+1] = 1.0;
projectionmatrix[2*4+2] = 16777215.0;
projectionmatrix[3*4+3] = 1.0;
BEGIN_RING(chan, kelvin, NV20TCL_PROJECTION_MATRIX(0), 16);
for (i = 0; i < 16; i++) {
OUT_RINGf (chan, projectionmatrix[i]);
}
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_RANGE_NEAR, 2);
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 16777216.0); /* [0, 1] scaled approx to [0, 2^24] */
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
OUT_RINGf (chan, 0.0); /* x-offset, w/2 + 1.031250 */
OUT_RINGf (chan, 0.0); /* y-offset, h/2 + 0.030762 */
OUT_RINGf (chan, 0.0);
OUT_RINGf (chan, 16777215.0);
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_SCALE_X, 4);
OUT_RINGf (chan, 0.0); /* no effect?, w/2 */
OUT_RINGf (chan, 0.0); /* no effect?, h/2 */
OUT_RINGf (chan, 16777215.0 * 0.5);
OUT_RINGf (chan, 65535.0);
FIRE_RING (chan);
}
struct pipe_context *
nv20_create(struct pipe_screen *pscreen, unsigned pctx_id)
{
struct nv20_screen *screen = nv20_screen(pscreen);
struct pipe_winsys *ws = pscreen->winsys;
struct nv20_context *nv20;
struct nouveau_winsys *nvws = screen->nvws;
nv20 = CALLOC(1, sizeof(struct nv20_context));
if (!nv20)
return NULL;
nv20->screen = screen;
nv20->pctx_id = pctx_id;
nv20->nvws = nvws;
nv20->pipe.winsys = ws;
nv20->pipe.screen = pscreen;
nv20->pipe.destroy = nv20_destroy;
nv20->pipe.draw_arrays = nv20_draw_arrays;
nv20->pipe.draw_elements = nv20_draw_elements;
nv20->pipe.clear = nv20_clear;
nv20->pipe.flush = nv20_flush;
nv20->pipe.is_texture_referenced = nouveau_is_texture_referenced;
nv20->pipe.is_buffer_referenced = nouveau_is_buffer_referenced;
nv20_init_surface_functions(nv20);
nv20_init_state_functions(nv20);
nv20->draw = draw_create();
assert(nv20->draw);
draw_set_rasterize_stage(nv20->draw, nv20_draw_vbuf_stage(nv20));
nv20_init_hwctx(nv20);
return &nv20->pipe;
}
src/gallium/drivers/nv20/nv20_context.h
-152
View File
@@ -1,152 +0,0 @@
#ifndef __NV20_CONTEXT_H__
#define __NV20_CONTEXT_H__
#include <stdio.h>
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_compiler.h"
#include "util/u_memory.h"
#include "util/u_math.h"
#include "draw/draw_vertex.h"
#include "nouveau/nouveau_winsys.h"
#include "nouveau/nouveau_gldefs.h"
#include "nouveau/nouveau_context.h"
#include "nv20_state.h"
#define NOUVEAU_ERR(fmt, args...) \
fprintf(stderr, "%s:%d - "fmt, __func__, __LINE__, ##args);
#define NOUVEAU_MSG(fmt, args...) \
fprintf(stderr, "nouveau: "fmt, ##args);
#define NV20_NEW_VERTPROG (1 << 0)
#define NV20_NEW_FRAGPROG (1 << 1)
#define NV20_NEW_VTXARRAYS (1 << 2)
#define NV20_NEW_BLEND (1 << 3)
#define NV20_NEW_BLENDCOL (1 << 4)
#define NV20_NEW_RAST (1 << 5)
#define NV20_NEW_DSA (1 << 6)
#define NV20_NEW_VIEWPORT (1 << 7)
#define NV20_NEW_SCISSOR (1 << 8)
#define NV20_NEW_FRAMEBUFFER (1 << 9)
#include "nv20_screen.h"
struct nv20_context {
struct pipe_context pipe;
struct nouveau_winsys *nvws;
struct nv20_screen *screen;
unsigned pctx_id;
struct draw_context *draw;
uint32_t dirty;
struct nv20_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
struct nv20_miptree *tex_miptree[PIPE_MAX_SAMPLERS];
unsigned dirty_samplers;
unsigned fp_samplers;
unsigned vp_samplers;
uint32_t rt_enable;
struct pipe_buffer *rt[4];
struct pipe_buffer *zeta;
uint32_t lma_offset;
struct nv20_blend_state *blend;
struct pipe_blend_color *blend_color;
struct nv20_rasterizer_state *rast;
struct nv20_depth_stencil_alpha_state *dsa;
struct pipe_viewport_state *viewport;
struct pipe_scissor_state *scissor;
struct pipe_framebuffer_state *framebuffer;
//struct pipe_buffer *constbuf[PIPE_SHADER_TYPES];
float *constbuf[PIPE_SHADER_TYPES][32][4];
unsigned constbuf_nr[PIPE_SHADER_TYPES];
struct vertex_info vertex_info;
struct {
struct pipe_buffer *buffer;
uint32_t format;
} tex[2];
unsigned vb_enable;
struct {
struct pipe_buffer *buffer;
unsigned delta;
} vb[16];
/* struct {
struct nouveau_resource *exec_heap;
struct nouveau_resource *data_heap;
struct nv20_vertex_program *active;
struct nv20_vertex_program *current;
} vertprog;
*/
struct {
struct nv20_fragment_program *active;
struct nv20_fragment_program *current;
struct pipe_buffer *constant_buf;
} fragprog;
struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
struct pipe_vertex_element vtxelt[PIPE_MAX_ATTRIBS];
};
static INLINE struct nv20_context *
nv20_context(struct pipe_context *pipe)
{
return (struct nv20_context *)pipe;
}
extern void nv20_init_state_functions(struct nv20_context *nv20);
extern void nv20_init_surface_functions(struct nv20_context *nv20);
extern void nv20_screen_init_miptree_functions(struct pipe_screen *pscreen);
/* nv20_clear.c */
extern void nv20_clear(struct pipe_context *pipe, unsigned buffers,
const float *rgba, double depth, unsigned stencil);
/* nv20_draw.c */
extern struct draw_stage *nv20_draw_render_stage(struct nv20_context *nv20);
/* nv20_fragprog.c */
extern void nv20_fragprog_bind(struct nv20_context *,
struct nv20_fragment_program *);
extern void nv20_fragprog_destroy(struct nv20_context *,
struct nv20_fragment_program *);
/* nv20_fragtex.c */
extern void nv20_fragtex_bind(struct nv20_context *);
/* nv20_prim_vbuf.c */
struct draw_stage *nv20_draw_vbuf_stage( struct nv20_context *nv20 );
extern void nv20_vtxbuf_bind(struct nv20_context* nv20);
/* nv20_state.c and friends */
extern void nv20_emit_hw_state(struct nv20_context *nv20);
extern void nv20_state_tex_update(struct nv20_context *nv20);
/* nv20_vbo.c */
extern void nv20_draw_arrays(struct pipe_context *, unsigned mode,
unsigned start, unsigned count);
extern void nv20_draw_elements( struct pipe_context *pipe,
struct pipe_buffer *indexBuffer,
unsigned indexSize,
unsigned prim, unsigned start, unsigned count);
#endif
src/gallium/drivers/nv20/nv20_fragprog.c
-21
View File
@@ -1,21 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_shader_tokens.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_util.h"
#include "nv20_context.h"
void
nv20_fragprog_bind(struct nv20_context *nv20, struct nv20_fragment_program *fp)
{
}
void
nv20_fragprog_destroy(struct nv20_context *nv20,
struct nv20_fragment_program *fp)
{
}
src/gallium/drivers/nv20/nv20_fragtex.c
-130
View File
@@ -1,130 +0,0 @@
#include "nv20_context.h"
#include "nouveau/nouveau_util.h"
#define _(m,tf) \
{ \
TRUE, \
PIPE_FORMAT_##m, \
NV20TCL_TX_FORMAT_FORMAT_##tf, \
}
struct nv20_texture_format {
boolean defined;
uint pipe;
int format;
};
static struct nv20_texture_format
nv20_texture_formats[] = {
_(A8R8G8B8_UNORM, A8R8G8B8),
_(A1R5G5B5_UNORM, A1R5G5B5),
_(A4R4G4B4_UNORM, A4R4G4B4),
_(L8_UNORM , L8 ),
_(A8_UNORM , A8 ),
_(A8L8_UNORM , A8L8 ),
/* _(RGB_DXT1 , DXT1, ), */
/* _(RGBA_DXT1 , DXT1, ), */
/* _(RGBA_DXT3 , DXT3, ), */
/* _(RGBA_DXT5 , DXT5, ), */
{},
};
static struct nv20_texture_format *
nv20_fragtex_format(uint pipe_format)
{
struct nv20_texture_format *tf = nv20_texture_formats;
while (tf->defined) {
if (tf->pipe == pipe_format)
return tf;
tf++;
}
return NULL;
}
static void
nv20_fragtex_build(struct nv20_context *nv20, int unit)
{
#if 0
struct nv20_sampler_state *ps = nv20->tex_sampler[unit];
struct nv20_miptree *nv20mt = nv20->tex_miptree[unit];
struct pipe_texture *pt = &nv20mt->base;
struct nv20_texture_format *tf;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
uint32_t txf, txs, txp;
tf = nv20_fragtex_format(pt->format);
if (!tf || !tf->defined) {
NOUVEAU_ERR("Unsupported texture format: 0x%x\n", pt->format);
return;
}
txf = tf->format << 8;
txf |= (pt->last_level + 1) << 16;
txf |= log2i(pt->width0) << 20;
txf |= log2i(pt->height0) << 24;
txf |= log2i(pt->depth0) << 28;
txf |= 8;
switch (pt->target) {
case PIPE_TEXTURE_CUBE:
txf |= NV10TCL_TX_FORMAT_CUBE_MAP;
/* fall-through */
case PIPE_TEXTURE_2D:
txf |= (2<<4);
break;
case PIPE_TEXTURE_1D:
txf |= (1<<4);
break;
default:
NOUVEAU_ERR("Unknown target %d\n", pt->target);
return;
}
BEGIN_RING(chan, kelvin, NV10TCL_TX_OFFSET(unit), 8);
OUT_RELOCl(chan, nouveau_bo(nv20mt->buffer), 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RELOCd(chan, nouveau_bo(nv20mt->buffer),txf,NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/);
OUT_RING (chan, ps->wrap);
OUT_RING (chan, 0x40000000); /* enable */
OUT_RING (chan, txs);
OUT_RING (chan, ps->filt | 0x2000 /* magic */);
OUT_RING (chan, (pt->width0 << 16) | pt->height0);
OUT_RING (chan, ps->bcol);
#endif
}
void
nv20_fragtex_bind(struct nv20_context *nv20)
{
#if 0
struct nv20_fragment_program *fp = nv20->fragprog.active;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
unsigned samplers, unit;
samplers = nv20->fp_samplers & ~fp->samplers;
while (samplers) {
unit = ffs(samplers) - 1;
samplers &= ~(1 << unit);
BEGIN_RING(chan, kelvin, NV10TCL_TX_ENABLE(unit), 1);
OUT_RING (chan, 0);
}
samplers = nv20->dirty_samplers & fp->samplers;
while (samplers) {
unit = ffs(samplers) - 1;
samplers &= ~(1 << unit);
nv20_fragtex_build(nv20, unit);
}
nv20->fp_samplers = fp->samplers;
#endif
}
src/gallium/drivers/nv20/nv20_miptree.c
-226
View File
@@ -1,226 +0,0 @@
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "util/u_inlines.h"
#include "util/u_format.h"
#include "util/u_math.h"
#include "nv20_context.h"
#include "nv20_screen.h"
#include "../nv04/nv04_surface_2d.h"
static void
nv20_miptree_layout(struct nv20_miptree *nv20mt)
{
struct pipe_texture *pt = &nv20mt->base;
uint width = pt->width0;
uint offset = 0;
int nr_faces, l, f;
uint wide_pitch = pt->tex_usage & (PIPE_TEXTURE_USAGE_SAMPLER |
PIPE_TEXTURE_USAGE_DEPTH_STENCIL |
PIPE_TEXTURE_USAGE_RENDER_TARGET |
PIPE_TEXTURE_USAGE_DISPLAY_TARGET |
PIPE_TEXTURE_USAGE_PRIMARY);
if (pt->target == PIPE_TEXTURE_CUBE) {
nr_faces = 6;
} else {
nr_faces = 1;
}
for (l = 0; l <= pt->last_level; l++) {
if (wide_pitch && (pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
nv20mt->level[l].pitch = align(util_format_get_stride(pt->format, pt->width0), 64);
else
nv20mt->level[l].pitch = util_format_get_stride(pt->format, width);
nv20mt->level[l].image_offset =
CALLOC(nr_faces, sizeof(unsigned));
width = u_minify(width, 1);
}
for (f = 0; f < nr_faces; f++) {
for (l = 0; l < pt->last_level; l++) {
nv20mt->level[l].image_offset[f] = offset;
if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR) &&
u_minify(pt->width0, l + 1) > 1 && u_minify(pt->height0, l + 1) > 1)
offset += align(nv20mt->level[l].pitch * u_minify(pt->height0, l), 64);
else
offset += nv20mt->level[l].pitch * u_minify(pt->height0, l);
}
nv20mt->level[l].image_offset[f] = offset;
offset += nv20mt->level[l].pitch * u_minify(pt->height0, l);
}
nv20mt->total_size = offset;
}
static struct pipe_texture *
nv20_miptree_blanket(struct pipe_screen *pscreen, const struct pipe_texture *pt,
const unsigned *stride, struct pipe_buffer *pb)
{
struct nv20_miptree *mt;
/* Only supports 2D, non-mipmapped textures for the moment */
if (pt->target != PIPE_TEXTURE_2D || pt->last_level != 0 ||
pt->depth0 != 1)
return NULL;
mt = CALLOC_STRUCT(nv20_miptree);
if (!mt)
return NULL;
mt->base = *pt;
pipe_reference_init(&mt->base.reference, 1);
mt->base.screen = pscreen;
mt->level[0].pitch = stride[0];
mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
pipe_buffer_reference(&mt->buffer, pb);
mt->bo = nouveau_bo(mt->buffer);
return &mt->base;
}
static struct pipe_texture *
nv20_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt)
{
struct nv20_miptree *mt;
unsigned buf_usage = PIPE_BUFFER_USAGE_PIXEL |
NOUVEAU_BUFFER_USAGE_TEXTURE;
mt = MALLOC(sizeof(struct nv20_miptree));
if (!mt)
return NULL;
mt->base = *pt;
pipe_reference_init(&mt->base.reference, 1);
mt->base.screen = screen;
/* Swizzled textures must be POT */
if (pt->width0 & (pt->width0 - 1) ||
pt->height0 & (pt->height0 - 1))
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else
if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY |
PIPE_TEXTURE_USAGE_DISPLAY_TARGET |
PIPE_TEXTURE_USAGE_DEPTH_STENCIL))
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else
if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC)
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
else {
switch (pt->format) {
/* TODO: Figure out which formats can be swizzled */
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_X8R8G8B8_UNORM:
case PIPE_FORMAT_R16_SNORM:
{
if (debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE))
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
break;
}
default:
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
}
}
if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC)
buf_usage |= PIPE_BUFFER_USAGE_CPU_READ_WRITE;
/* apparently we can't render to swizzled surfaces smaller than 64 bytes, so make them linear.
* If the user did not ask for a render target, they can still render to it, but it will cost them an extra copy.
* This also happens for small mipmaps of large textures. */
if (pt->tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET && util_format_get_stride(pt->format, pt->width0) < 64)
mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
nv20_miptree_layout(mt);
mt->buffer = screen->buffer_create(screen, 256, buf_usage, mt->total_size);
if (!mt->buffer) {
FREE(mt);
return NULL;
}
mt->bo = nouveau_bo(mt->buffer);
return &mt->base;
}
static void
nv20_miptree_destroy(struct pipe_texture *pt)
{
struct nv20_miptree *nv20mt = (struct nv20_miptree *)pt;
int l;
pipe_buffer_reference(&nv20mt->buffer, NULL);
for (l = 0; l <= pt->last_level; l++) {
if (nv20mt->level[l].image_offset)
FREE(nv20mt->level[l].image_offset);
}
}
static struct pipe_surface *
nv20_miptree_surface_get(struct pipe_screen *screen, struct pipe_texture *pt,
unsigned face, unsigned level, unsigned zslice,
unsigned flags)
{
struct nv20_miptree *nv20mt = (struct nv20_miptree *)pt;
struct nv04_surface *ns;
ns = CALLOC_STRUCT(nv04_surface);
if (!ns)
return NULL;
pipe_texture_reference(&ns->base.texture, pt);
ns->base.format = pt->format;
ns->base.width = u_minify(pt->width0, level);
ns->base.height = u_minify(pt->height0, level);
ns->base.usage = flags;
pipe_reference_init(&ns->base.reference, 1);
ns->base.face = face;
ns->base.level = level;
ns->base.zslice = zslice;
ns->pitch = nv20mt->level[level].pitch;
if (pt->target == PIPE_TEXTURE_CUBE) {
ns->base.offset = nv20mt->level[level].image_offset[face];
} else
if (pt->target == PIPE_TEXTURE_3D) {
ns->base.offset = nv20mt->level[level].image_offset[zslice];
} else {
ns->base.offset = nv20mt->level[level].image_offset[0];
}
/* create a linear temporary that we can render into if necessary.
* Note that ns->pitch is always a multiple of 64 for linear surfaces and swizzled surfaces are POT, so
* ns->pitch & 63 is equivalent to (ns->pitch < 64 && swizzled)*/
if((ns->pitch & 63) && (ns->base.usage & (PIPE_BUFFER_USAGE_GPU_WRITE | NOUVEAU_BUFFER_USAGE_NO_RENDER)) == PIPE_BUFFER_USAGE_GPU_WRITE)
return &nv04_surface_wrap_for_render(screen, ((struct nv20_screen*)screen)->eng2d, ns)->base;
return &ns->base;
}
static void
nv20_miptree_surface_destroy(struct pipe_surface *ps)
{
struct nv04_surface* ns = (struct nv04_surface*)ps;
if(ns->backing)
{
struct nv20_screen* screen = (struct nv20_screen*)ps->texture->screen;
if(ns->backing->base.usage & PIPE_BUFFER_USAGE_GPU_WRITE)
screen->eng2d->copy(screen->eng2d, &ns->backing->base, 0, 0, ps, 0, 0, ns->base.width, ns->base.height);
nv20_miptree_surface_destroy(&ns->backing->base);
}
pipe_texture_reference(&ps->texture, NULL);
FREE(ps);
}
void nv20_screen_init_miptree_functions(struct pipe_screen *pscreen)
{
pscreen->texture_create = nv20_miptree_create;
pscreen->texture_blanket = nv20_miptree_blanket;
pscreen->texture_destroy = nv20_miptree_destroy;
pscreen->get_tex_surface = nv20_miptree_surface_get;
pscreen->tex_surface_destroy = nv20_miptree_surface_destroy;
}
src/gallium/drivers/nv20/nv20_prim_vbuf.c
-440
View File
@@ -1,440 +0,0 @@
/**************************************************************************
*
* Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/**
* \file
* Build post-transformation, post-clipping vertex buffers and element
* lists by hooking into the end of the primitive pipeline and
* manipulating the vertex_id field in the vertex headers.
*
* XXX: work in progress
*
* \author José Fonseca <jrfonseca@tungstengraphics.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
#include "util/u_debug.h"
#include "util/u_inlines.h"
#include "util/u_simple_screen.h"
#include "nv20_context.h"
#include "nv20_state.h"
#include "draw/draw_vbuf.h"
/**
* Primitive renderer for nv20.
*/
struct nv20_vbuf_render {
struct vbuf_render base;
struct nv20_context *nv20;
/** Vertex buffer in VRAM */
struct pipe_buffer *pbuffer;
/** Vertex buffer in normal memory */
void *mbuffer;
/** Vertex size in bytes */
/*unsigned vertex_size;*/
/** Hardware primitive */
unsigned hwprim;
};
/**
* Basically a cast wrapper.
*/
static INLINE struct nv20_vbuf_render *
nv20_vbuf_render(struct vbuf_render *render)
{
assert(render);
return (struct nv20_vbuf_render *)render;
}
void nv20_vtxbuf_bind( struct nv20_context* nv20 )
{
#if 0
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
int i;
for(i = 0; i < NV20TCL_VTXBUF_ADDRESS__SIZE; i++) {
BEGIN_RING(chan, kelvin, NV20TCL_VTXBUF_ADDRESS(i), 1);
OUT_RING(chan, 0/*nv20->vtxbuf*/);
BEGIN_RING(chan, kelvin, NV20TCL_VTXFMT(i) ,1);
OUT_RING(chan, 0/*XXX*/);
}
#endif
}
static const struct vertex_info *
nv20_vbuf_render_get_vertex_info( struct vbuf_render *render )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
struct nv20_context *nv20 = nv20_render->nv20;
nv20_emit_hw_state(nv20);
return &nv20->vertex_info;
}
static void *
nv20__allocate_mbuffer(struct nv20_vbuf_render *nv20_render, size_t size)
{
nv20_render->mbuffer = MALLOC(size);
return nv20_render->mbuffer;
}
static void
nv20__allocate_pbuffer(struct nv20_vbuf_render *nv20_render, size_t size)
{
struct pipe_screen *screen = nv20_render->nv20->pipe.screen;
nv20_render->pbuffer = screen->buffer_create(screen, 64,
PIPE_BUFFER_USAGE_VERTEX, size);
}
static boolean
nv20_vbuf_render_allocate_vertices( struct vbuf_render *render,
ushort vertex_size,
ushort nr_vertices )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
size_t size = (size_t)vertex_size * (size_t)nr_vertices;
void *buf;
assert(!nv20_render->pbuffer);
assert(!nv20_render->mbuffer);
/*
* For small amount of vertices, don't bother with pipe vertex
* buffer, the data will be passed directly via the fifo.
*/
/* XXX: Pipe vertex buffers don't work. */
if (0 && size > 16 * 1024) {
nv20__allocate_pbuffer(nv20_render, size);
/* umm yeah so this is ugly */
buf = nv20_render->pbuffer;
} else {
buf = nv20__allocate_mbuffer(nv20_render, size);
}
if (buf)
nv20_render->nv20->dirty |= NV20_NEW_VTXARRAYS;
return buf ? TRUE : FALSE;
}
static void *
nv20_vbuf_render_map_vertices( struct vbuf_render *render )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
struct pipe_screen *pscreen = nv20_render->nv20->pipe.screen;
if (nv20_render->pbuffer) {
return pipe_buffer_map(pscreen, nv20_render->pbuffer,
PIPE_BUFFER_USAGE_CPU_WRITE);
} else if (nv20_render->mbuffer) {
return nv20_render->mbuffer;
} else
assert(0);
/* warnings be gone */
return NULL;
}
static void
nv20_vbuf_render_unmap_vertices( struct vbuf_render *render,
ushort min_index,
ushort max_index )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
struct pipe_screen *pscreen = nv20_render->nv20->pipe.screen;
if (nv20_render->pbuffer)
pipe_buffer_unmap(pscreen, nv20_render->pbuffer);
}
static boolean
nv20_vbuf_render_set_primitive( struct vbuf_render *render,
unsigned prim )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
unsigned hwp = nvgl_primitive(prim);
if (hwp == 0)
return FALSE;
nv20_render->hwprim = hwp;
return TRUE;
}
static uint32_t
nv20__vtxhwformat(unsigned stride, unsigned fields, unsigned type)
{
return (stride << NV20TCL_VTXFMT_STRIDE_SHIFT) |
(fields << NV20TCL_VTXFMT_SIZE_SHIFT) |
(type << NV20TCL_VTXFMT_TYPE_SHIFT);
}
static unsigned
nv20__emit_format(struct nv20_context *nv20, enum attrib_emit type, int hwattr)
{
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
uint32_t hwfmt = 0;
unsigned fields;
switch (type) {
case EMIT_OMIT:
hwfmt = nv20__vtxhwformat(0, 0, 2);
fields = 0;
break;
case EMIT_1F:
hwfmt = nv20__vtxhwformat(4, 1, 2);
fields = 1;
break;
case EMIT_2F:
hwfmt = nv20__vtxhwformat(8, 2, 2);
fields = 2;
break;
case EMIT_3F:
hwfmt = nv20__vtxhwformat(12, 3, 2);
fields = 3;
break;
case EMIT_4F:
hwfmt = nv20__vtxhwformat(16, 4, 2);
fields = 4;
break;
default:
NOUVEAU_ERR("unhandled attrib_emit %d\n", type);
return 0;
}
BEGIN_RING(chan, kelvin, NV20TCL_VTXFMT(hwattr), 1);
OUT_RING(chan, hwfmt);
return fields;
}
static unsigned
nv20__emit_vertex_array_format(struct nv20_context *nv20)
{
struct vertex_info *vinfo = &nv20->vertex_info;
int hwattr = NV20TCL_VTXFMT__SIZE;
int attr = 0;
unsigned nr_fields = 0;
while (hwattr-- > 0) {
if (vinfo->hwfmt[0] & (1 << hwattr)) {
nr_fields += nv20__emit_format(nv20,
vinfo->attrib[attr].emit, hwattr);
attr++;
} else
nv20__emit_format(nv20, EMIT_OMIT, hwattr);
}
return nr_fields;
}
static void
nv20__draw_mbuffer(struct nv20_vbuf_render *nv20_render,
const ushort *indices,
uint nr_indices)
{
struct nv20_context *nv20 = nv20_render->nv20;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
struct vertex_info *vinfo = &nv20->vertex_info;
unsigned nr_fields;
int max_push;
ubyte *data = nv20_render->mbuffer;
int vsz = 4 * vinfo->size;
nr_fields = nv20__emit_vertex_array_format(nv20);
BEGIN_RING(chan, kelvin, NV20TCL_VERTEX_BEGIN_END, 1);
OUT_RING(chan, nv20_render->hwprim);
max_push = 1200 / nr_fields;
while (nr_indices) {
int i;
int push = MIN2(nr_indices, max_push);
BEGIN_RING_NI(chan, kelvin, NV20TCL_VERTEX_DATA, push * nr_fields);
for (i = 0; i < push; i++) {
/* XXX: fixme to handle other than floats? */
int f = nr_fields;
float *attrv = (float*)&data[indices[i] * vsz];
while (f-- > 0)
OUT_RINGf(chan, *attrv++);
}
nr_indices -= push;
indices += push;
}
BEGIN_RING(chan, kelvin, NV20TCL_VERTEX_BEGIN_END, 1);
OUT_RING(chan, NV20TCL_VERTEX_BEGIN_END_STOP);
}
static void
nv20__draw_pbuffer(struct nv20_vbuf_render *nv20_render,
const ushort *indices,
uint nr_indices)
{
struct nv20_context *nv20 = nv20_render->nv20;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
int push, i;
NOUVEAU_ERR("nv20__draw_pbuffer: this path is broken.\n");
BEGIN_RING(chan, kelvin, NV10TCL_VERTEX_ARRAY_OFFSET_POS, 1);
OUT_RELOCl(chan, nouveau_bo(nv20_render->pbuffer), 0,
NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_RING(chan, kelvin, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);
OUT_RING(chan, nv20_render->hwprim);
if (nr_indices & 1) {
BEGIN_RING(chan, kelvin, NV10TCL_VB_ELEMENT_U32, 1);
OUT_RING (chan, indices[0]);
indices++; nr_indices--;
}
while (nr_indices) {
// XXX too big/small ? check the size
push = MIN2(nr_indices, 1200 * 2);
BEGIN_RING_NI(chan, kelvin, NV10TCL_VB_ELEMENT_U16, push >> 1);
for (i = 0; i < push; i+=2)
OUT_RING(chan, (indices[i+1] << 16) | indices[i]);
nr_indices -= push;
indices += push;
}
BEGIN_RING(chan, kelvin, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);
OUT_RING (chan, 0);
}
static void
nv20_vbuf_render_draw( struct vbuf_render *render,
const ushort *indices,
uint nr_indices)
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
nv20_emit_hw_state(nv20_render->nv20);
if (nv20_render->pbuffer)
nv20__draw_pbuffer(nv20_render, indices, nr_indices);
else if (nv20_render->mbuffer)
nv20__draw_mbuffer(nv20_render, indices, nr_indices);
else
assert(0);
}
static void
nv20_vbuf_render_release_vertices( struct vbuf_render *render )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
struct nv20_context *nv20 = nv20_render->nv20;
if (nv20_render->pbuffer) {
pipe_buffer_reference(&nv20_render->pbuffer, NULL);
} else if (nv20_render->mbuffer) {
FREE(nv20_render->mbuffer);
nv20_render->mbuffer = NULL;
} else
assert(0);
}
static void
nv20_vbuf_render_destroy( struct vbuf_render *render )
{
struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render);
assert(!nv20_render->pbuffer);
assert(!nv20_render->mbuffer);
FREE(nv20_render);
}
/**
* Create a new primitive render.
*/
static struct vbuf_render *
nv20_vbuf_render_create( struct nv20_context *nv20 )
{
struct nv20_vbuf_render *nv20_render = CALLOC_STRUCT(nv20_vbuf_render);
nv20_render->nv20 = nv20;
nv20_render->base.max_vertex_buffer_bytes = 16*1024;
nv20_render->base.max_indices = 1024;
nv20_render->base.get_vertex_info = nv20_vbuf_render_get_vertex_info;
nv20_render->base.allocate_vertices =
nv20_vbuf_render_allocate_vertices;
nv20_render->base.map_vertices = nv20_vbuf_render_map_vertices;
nv20_render->base.unmap_vertices = nv20_vbuf_render_unmap_vertices;
nv20_render->base.set_primitive = nv20_vbuf_render_set_primitive;
nv20_render->base.draw = nv20_vbuf_render_draw;
nv20_render->base.release_vertices = nv20_vbuf_render_release_vertices;
nv20_render->base.destroy = nv20_vbuf_render_destroy;
return &nv20_render->base;
}
/**
* Create a new primitive vbuf/render stage.
*/
struct draw_stage *nv20_draw_vbuf_stage( struct nv20_context *nv20 )
{
struct vbuf_render *render;
struct draw_stage *stage;
render = nv20_vbuf_render_create(nv20);
if(!render)
return NULL;
stage = draw_vbuf_stage( nv20->draw, render );
if(!stage) {
render->destroy(render);
return NULL;
}
return stage;
}
src/gallium/drivers/nv20/nv20_screen.c
-204
View File
@@ -1,204 +0,0 @@
#include "pipe/p_screen.h"
#include "nv20_context.h"
#include "nv20_screen.h"
static int
nv20_screen_get_param(struct pipe_screen *screen, int param)
{
switch (param) {
case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
return 2;
case PIPE_CAP_NPOT_TEXTURES:
return 0;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 0;
case PIPE_CAP_GLSL:
return 0;
case PIPE_CAP_ANISOTROPIC_FILTER:
return 1;
case PIPE_CAP_POINT_SPRITE:
return 0;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 1;
case PIPE_CAP_OCCLUSION_QUERY:
return 0;
case PIPE_CAP_TEXTURE_SHADOW_MAP:
return 0;
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
return 12;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 0;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 12;
case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
return 0;
case PIPE_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
return 0;
case NOUVEAU_CAP_HW_VTXBUF:
case NOUVEAU_CAP_HW_IDXBUF:
return 0;
case PIPE_CAP_INDEP_BLEND_ENABLE:
return 0;
case PIPE_CAP_INDEP_BLEND_FUNC:
return 0;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
return 1;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
}
}
static float
nv20_screen_get_paramf(struct pipe_screen *screen, int param)
{
switch (param) {
case PIPE_CAP_MAX_LINE_WIDTH:
case PIPE_CAP_MAX_LINE_WIDTH_AA:
return 10.0;
case PIPE_CAP_MAX_POINT_WIDTH:
case PIPE_CAP_MAX_POINT_WIDTH_AA:
return 64.0;
case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
return 2.0;
case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
return 4.0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0.0;
}
}
static boolean
nv20_screen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
unsigned tex_usage, unsigned geom_flags)
{
if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
return TRUE;
default:
break;
}
} else
if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
switch (format) {
case PIPE_FORMAT_Z24S8_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z16_UNORM:
return TRUE;
default:
break;
}
} else {
switch (format) {
case PIPE_FORMAT_A8R8G8B8_UNORM:
case PIPE_FORMAT_A1R5G5B5_UNORM:
case PIPE_FORMAT_A4R4G4B4_UNORM:
case PIPE_FORMAT_R5G6B5_UNORM:
case PIPE_FORMAT_L8_UNORM:
case PIPE_FORMAT_A8_UNORM:
case PIPE_FORMAT_I8_UNORM:
return TRUE;
default:
break;
}
}
return FALSE;
}
static void
nv20_screen_destroy(struct pipe_screen *pscreen)
{
struct nv20_screen *screen = nv20_screen(pscreen);
nouveau_notifier_free(&screen->sync);
nouveau_grobj_free(&screen->kelvin);
nv04_surface_2d_takedown(&screen->eng2d);
nouveau_screen_fini(&screen->base);
FREE(pscreen);
}
static struct pipe_buffer *
nv20_surface_buffer(struct pipe_surface *surf)
{
struct nv20_miptree *mt = (struct nv20_miptree *)surf->texture;
return mt->buffer;
}
struct pipe_screen *
nv20_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
{
struct nv20_screen *screen = CALLOC_STRUCT(nv20_screen);
struct nouveau_channel *chan;
struct pipe_screen *pscreen;
unsigned kelvin_class = 0;
int ret;
if (!screen)
return NULL;
pscreen = &screen->base.base;
ret = nouveau_screen_init(&screen->base, dev);
if (ret) {
nv20_screen_destroy(pscreen);
return NULL;
}
chan = screen->base.channel;
pscreen->winsys = ws;
pscreen->destroy = nv20_screen_destroy;
pscreen->get_param = nv20_screen_get_param;
pscreen->get_paramf = nv20_screen_get_paramf;
pscreen->is_format_supported = nv20_screen_is_format_supported;
nv20_screen_init_miptree_functions(pscreen);
nv20_screen_init_transfer_functions(pscreen);
/* 3D object */
if (dev->chipset >= 0x25)
kelvin_class = NV25TCL;
else if (dev->chipset >= 0x20)
kelvin_class = NV20TCL;
if (!kelvin_class || dev->chipset >= 0x30) {
NOUVEAU_ERR("Unknown nv2x chipset: nv%02x\n", dev->chipset);
return NULL;
}
ret = nouveau_grobj_alloc(chan, 0xbeef0097, kelvin_class,
&screen->kelvin);
if (ret) {
NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
return FALSE;
}
/* 2D engine setup */
screen->eng2d = nv04_surface_2d_init(&screen->base);
screen->eng2d->buf = nv20_surface_buffer;
/* Notifier for sync purposes */
ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
if (ret) {
NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
nv20_screen_destroy(pscreen);
return NULL;
}
return pscreen;
}
src/gallium/drivers/nv20/nv20_screen.h
-28
View File
@@ -1,28 +0,0 @@
#ifndef __NV20_SCREEN_H__
#define __NV20_SCREEN_H__
#include "nouveau/nouveau_screen.h"
#include "nv04/nv04_surface_2d.h"
struct nv20_screen {
struct nouveau_screen base;
struct nouveau_winsys *nvws;
/* HW graphics objects */
struct nv04_surface_2d *eng2d;
struct nouveau_grobj *kelvin;
struct nouveau_notifier *sync;
};
static INLINE struct nv20_screen *
nv20_screen(struct pipe_screen *screen)
{
return (struct nv20_screen *)screen;
}
void
nv20_screen_init_transfer_functions(struct pipe_screen *pscreen);
#endif
src/gallium/drivers/nv20/nv20_state.c
-583
View File
@@ -1,583 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "pipe/p_shader_tokens.h"
#include "util/u_inlines.h"
#include "tgsi/tgsi_parse.h"
#include "nv20_context.h"
#include "nv20_state.h"
static void *
nv20_blend_state_create(struct pipe_context *pipe,
const struct pipe_blend_state *cso)
{
struct nv20_blend_state *cb;
cb = MALLOC(sizeof(struct nv20_blend_state));
cb->b_enable = cso->rt[0].blend_enable ? 1 : 0;
cb->b_srcfunc = ((nvgl_blend_func(cso->rt[0].alpha_src_factor)<<16) |
(nvgl_blend_func(cso->rt[0].rgb_src_factor)));
cb->b_dstfunc = ((nvgl_blend_func(cso->rt[0].alpha_dst_factor)<<16) |
(nvgl_blend_func(cso->rt[0].rgb_dst_factor)));
cb->c_mask = (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01<<24) : 0) |
((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01<<16) : 0) |
((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) |
((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01<< 0) : 0));
cb->d_enable = cso->dither ? 1 : 0;
return (void *)cb;
}
static void
nv20_blend_state_bind(struct pipe_context *pipe, void *blend)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->blend = (struct nv20_blend_state*)blend;
nv20->dirty |= NV20_NEW_BLEND;
}
static void
nv20_blend_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static INLINE unsigned
wrap_mode(unsigned wrap) {
unsigned ret;
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
ret = NV20TCL_TX_WRAP_S_REPEAT;
break;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
ret = NV20TCL_TX_WRAP_S_MIRRORED_REPEAT;
break;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
ret = NV20TCL_TX_WRAP_S_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
ret = NV20TCL_TX_WRAP_S_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_CLAMP:
ret = NV20TCL_TX_WRAP_S_CLAMP;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP:
default:
NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
ret = NV20TCL_TX_WRAP_S_REPEAT;
break;
}
return (ret >> NV20TCL_TX_WRAP_S_SHIFT);
}
static void *
nv20_sampler_state_create(struct pipe_context *pipe,
const struct pipe_sampler_state *cso)
{
struct nv20_sampler_state *ps;
uint32_t filter = 0;
ps = MALLOC(sizeof(struct nv20_sampler_state));
ps->wrap = ((wrap_mode(cso->wrap_s) << NV20TCL_TX_WRAP_S_SHIFT) |
(wrap_mode(cso->wrap_t) << NV20TCL_TX_WRAP_T_SHIFT));
ps->en = 0;
if (cso->max_anisotropy > 1.0) {
/* no idea, binary driver sets it, works without it.. meh.. */
ps->wrap |= (1 << 5);
/* if (cso->max_anisotropy >= 8.0) {
ps->en |= NV20TCL_TX_ENABLE_ANISO_8X;
} else
if (cso->max_anisotropy >= 4.0) {
ps->en |= NV20TCL_TX_ENABLE_ANISO_4X;
} else {
ps->en |= NV20TCL_TX_ENABLE_ANISO_2X;
}*/
}
switch (cso->mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
filter |= NV20TCL_TX_FILTER_MAGNIFY_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
filter |= NV20TCL_TX_FILTER_MAGNIFY_NEAREST;
break;
}
switch (cso->min_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |=
NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV20TCL_TX_FILTER_MINIFY_LINEAR;
break;
}
break;
case PIPE_TEX_FILTER_NEAREST:
default:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |=
NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |=
NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV20TCL_TX_FILTER_MINIFY_NEAREST;
break;
}
break;
}
ps->filt = filter;
/* if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
switch (cso->compare_func) {
case PIPE_FUNC_NEVER:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_NEVER;
break;
case PIPE_FUNC_GREATER:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_GREATER;
break;
case PIPE_FUNC_EQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_EQUAL;
break;
case PIPE_FUNC_GEQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_GEQUAL;
break;
case PIPE_FUNC_LESS:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_LESS;
break;
case PIPE_FUNC_NOTEQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_NOTEQUAL;
break;
case PIPE_FUNC_LEQUAL:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_LEQUAL;
break;
case PIPE_FUNC_ALWAYS:
ps->wrap |= NV10TCL_TX_WRAP_RCOMP_ALWAYS;
break;
default:
break;
}
}*/
ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
(float_to_ubyte(cso->border_color[0]) << 16) |
(float_to_ubyte(cso->border_color[1]) << 8) |
(float_to_ubyte(cso->border_color[2]) << 0));
return (void *)ps;
}
static void
nv20_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
{
struct nv20_context *nv20 = nv20_context(pipe);
unsigned unit;
for (unit = 0; unit < nr; unit++) {
nv20->tex_sampler[unit] = sampler[unit];
nv20->dirty_samplers |= (1 << unit);
}
}
static void
nv20_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static void
nv20_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
struct pipe_texture **miptree)
{
struct nv20_context *nv20 = nv20_context(pipe);
unsigned unit;
for (unit = 0; unit < nr; unit++) {
nv20->tex_miptree[unit] = (struct nv20_miptree *)miptree[unit];
nv20->dirty_samplers |= (1 << unit);
}
}
static void *
nv20_rasterizer_state_create(struct pipe_context *pipe,
const struct pipe_rasterizer_state *cso)
{
struct nv20_rasterizer_state *rs;
int i;
/*XXX: ignored:
* light_twoside
* offset_cw/ccw -nohw
* scissor
* point_smooth -nohw
* multisample
* offset_units / offset_scale
*/
rs = MALLOC(sizeof(struct nv20_rasterizer_state));
rs->templ = cso;
rs->shade_model = cso->flatshade ? NV20TCL_SHADE_MODEL_FLAT :
NV20TCL_SHADE_MODEL_SMOOTH;
rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff;
rs->line_smooth_en = cso->line_smooth ? 1 : 0;
/* XXX: nv20 and nv25 different! */
rs->point_size = *(uint32_t*)&cso->point_size;
rs->poly_smooth_en = cso->poly_smooth ? 1 : 0;
if (cso->front_winding == PIPE_WINDING_CCW) {
rs->front_face = NV20TCL_FRONT_FACE_CCW;
rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw);
rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw);
} else {
rs->front_face = NV20TCL_FRONT_FACE_CW;
rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw);
rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw);
}
switch (cso->cull_mode) {
case PIPE_WINDING_CCW:
rs->cull_face_en = 1;
if (cso->front_winding == PIPE_WINDING_CCW)
rs->cull_face = NV20TCL_CULL_FACE_FRONT;
else
rs->cull_face = NV20TCL_CULL_FACE_BACK;
break;
case PIPE_WINDING_CW:
rs->cull_face_en = 1;
if (cso->front_winding == PIPE_WINDING_CW)
rs->cull_face = NV20TCL_CULL_FACE_FRONT;
else
rs->cull_face = NV20TCL_CULL_FACE_BACK;
break;
case PIPE_WINDING_BOTH:
rs->cull_face_en = 1;
rs->cull_face = NV20TCL_CULL_FACE_FRONT_AND_BACK;
break;
case PIPE_WINDING_NONE:
default:
rs->cull_face_en = 0;
rs->cull_face = 0;
break;
}
if (cso->point_sprite) {
rs->point_sprite = (1 << 0);
for (i = 0; i < 8; i++) {
if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE)
rs->point_sprite |= (1 << (8 + i));
}
} else {
rs->point_sprite = 0;
}
return (void *)rs;
}
static void
nv20_rasterizer_state_bind(struct pipe_context *pipe, void *rast)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->rast = (struct nv20_rasterizer_state*)rast;
draw_set_rasterizer_state(nv20->draw, (nv20->rast ? nv20->rast->templ : NULL));
nv20->dirty |= NV20_NEW_RAST;
}
static void
nv20_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static void *
nv20_depth_stencil_alpha_state_create(struct pipe_context *pipe,
const struct pipe_depth_stencil_alpha_state *cso)
{
struct nv20_depth_stencil_alpha_state *hw;
hw = MALLOC(sizeof(struct nv20_depth_stencil_alpha_state));
hw->depth.func = nvgl_comparison_op(cso->depth.func);
hw->depth.write_enable = cso->depth.writemask ? 1 : 0;
hw->depth.test_enable = cso->depth.enabled ? 1 : 0;
hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0;
hw->stencil.wmask = cso->stencil[0].writemask;
hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func);
hw->stencil.ref = cso->stencil[0].ref_value;
hw->stencil.vmask = cso->stencil[0].valuemask;
hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op);
hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op);
hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op);
hw->alpha.enabled = cso->alpha.enabled ? 1 : 0;
hw->alpha.func = nvgl_comparison_op(cso->alpha.func);
hw->alpha.ref = float_to_ubyte(cso->alpha.ref_value);
return (void *)hw;
}
static void
nv20_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *dsa)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->dsa = (struct nv20_depth_stencil_alpha_state*)dsa;
nv20->dirty |= NV20_NEW_DSA;
}
static void
nv20_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
{
FREE(hwcso);
}
static void *
nv20_vp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *templ)
{
struct nv20_context *nv20 = nv20_context(pipe);
return draw_create_vertex_shader(nv20->draw, templ);
}
static void
nv20_vp_state_bind(struct pipe_context *pipe, void *shader)
{
struct nv20_context *nv20 = nv20_context(pipe);
draw_bind_vertex_shader(nv20->draw, (struct draw_vertex_shader *) shader);
nv20->dirty |= NV20_NEW_VERTPROG;
}
static void
nv20_vp_state_delete(struct pipe_context *pipe, void *shader)
{
struct nv20_context *nv20 = nv20_context(pipe);
draw_delete_vertex_shader(nv20->draw, (struct draw_vertex_shader *) shader);
}
static void *
nv20_fp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
struct nv20_fragment_program *fp;
fp = CALLOC(1, sizeof(struct nv20_fragment_program));
fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
tgsi_scan_shader(cso->tokens, &fp->info);
return (void *)fp;
}
static void
nv20_fp_state_bind(struct pipe_context *pipe, void *hwcso)
{
struct nv20_context *nv20 = nv20_context(pipe);
struct nv20_fragment_program *fp = hwcso;
nv20->fragprog.current = fp;
nv20->dirty |= NV20_NEW_FRAGPROG;
}
static void
nv20_fp_state_delete(struct pipe_context *pipe, void *hwcso)
{
struct nv20_context *nv20 = nv20_context(pipe);
struct nv20_fragment_program *fp = hwcso;
nv20_fragprog_destroy(nv20, fp);
FREE((void*)fp->pipe.tokens);
FREE(fp);
}
static void
nv20_set_blend_color(struct pipe_context *pipe,
const struct pipe_blend_color *bcol)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->blend_color = (struct pipe_blend_color*)bcol;
nv20->dirty |= NV20_NEW_BLENDCOL;
}
static void
nv20_set_clip_state(struct pipe_context *pipe,
const struct pipe_clip_state *clip)
{
struct nv20_context *nv20 = nv20_context(pipe);
draw_set_clip_state(nv20->draw, clip);
}
static void
nv20_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
struct pipe_buffer *buf )
{
struct nv20_context *nv20 = nv20_context(pipe);
struct pipe_screen *pscreen = pipe->screen;
assert(shader < PIPE_SHADER_TYPES);
assert(index == 0);
if (buf) {
void *mapped;
if (buf->size &&
(mapped = pipe_buffer_map(pscreen, buf, PIPE_BUFFER_USAGE_CPU_READ)))
{
memcpy(nv20->constbuf[shader], mapped, buf->size);
nv20->constbuf_nr[shader] =
buf->size / (4 * sizeof(float));
pipe_buffer_unmap(pscreen, buf);
}
}
}
static void
nv20_set_framebuffer_state(struct pipe_context *pipe,
const struct pipe_framebuffer_state *fb)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->framebuffer = (struct pipe_framebuffer_state*)fb;
nv20->dirty |= NV20_NEW_FRAMEBUFFER;
}
static void
nv20_set_polygon_stipple(struct pipe_context *pipe,
const struct pipe_poly_stipple *stipple)
{
NOUVEAU_ERR("line stipple hahaha\n");
}
static void
nv20_set_scissor_state(struct pipe_context *pipe,
const struct pipe_scissor_state *s)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->scissor = (struct pipe_scissor_state*)s;
nv20->dirty |= NV20_NEW_SCISSOR;
}
static void
nv20_set_viewport_state(struct pipe_context *pipe,
const struct pipe_viewport_state *vpt)
{
struct nv20_context *nv20 = nv20_context(pipe);
nv20->viewport = (struct pipe_viewport_state*)vpt;
draw_set_viewport_state(nv20->draw, nv20->viewport);
nv20->dirty |= NV20_NEW_VIEWPORT;
}
static void
nv20_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
const struct pipe_vertex_buffer *vb)
{
struct nv20_context *nv20 = nv20_context(pipe);
memcpy(nv20->vtxbuf, vb, sizeof(*vb) * count);
nv20->dirty |= NV20_NEW_VTXARRAYS;
draw_set_vertex_buffers(nv20->draw, count, vb);
}
static void
nv20_set_vertex_elements(struct pipe_context *pipe, unsigned count,
const struct pipe_vertex_element *ve)
{
struct nv20_context *nv20 = nv20_context(pipe);
memcpy(nv20->vtxelt, ve, sizeof(*ve) * count);
nv20->dirty |= NV20_NEW_VTXARRAYS;
draw_set_vertex_elements(nv20->draw, count, ve);
}
void
nv20_init_state_functions(struct nv20_context *nv20)
{
nv20->pipe.create_blend_state = nv20_blend_state_create;
nv20->pipe.bind_blend_state = nv20_blend_state_bind;
nv20->pipe.delete_blend_state = nv20_blend_state_delete;
nv20->pipe.create_sampler_state = nv20_sampler_state_create;
nv20->pipe.bind_fragment_sampler_states = nv20_sampler_state_bind;
nv20->pipe.delete_sampler_state = nv20_sampler_state_delete;
nv20->pipe.set_fragment_sampler_textures = nv20_set_sampler_texture;
nv20->pipe.create_rasterizer_state = nv20_rasterizer_state_create;
nv20->pipe.bind_rasterizer_state = nv20_rasterizer_state_bind;
nv20->pipe.delete_rasterizer_state = nv20_rasterizer_state_delete;
nv20->pipe.create_depth_stencil_alpha_state =
nv20_depth_stencil_alpha_state_create;
nv20->pipe.bind_depth_stencil_alpha_state =
nv20_depth_stencil_alpha_state_bind;
nv20->pipe.delete_depth_stencil_alpha_state =
nv20_depth_stencil_alpha_state_delete;
nv20->pipe.create_vs_state = nv20_vp_state_create;
nv20->pipe.bind_vs_state = nv20_vp_state_bind;
nv20->pipe.delete_vs_state = nv20_vp_state_delete;
nv20->pipe.create_fs_state = nv20_fp_state_create;
nv20->pipe.bind_fs_state = nv20_fp_state_bind;
nv20->pipe.delete_fs_state = nv20_fp_state_delete;
nv20->pipe.set_blend_color = nv20_set_blend_color;
nv20->pipe.set_clip_state = nv20_set_clip_state;
nv20->pipe.set_constant_buffer = nv20_set_constant_buffer;
nv20->pipe.set_framebuffer_state = nv20_set_framebuffer_state;
nv20->pipe.set_polygon_stipple = nv20_set_polygon_stipple;
nv20->pipe.set_scissor_state = nv20_set_scissor_state;
nv20->pipe.set_viewport_state = nv20_set_viewport_state;
nv20->pipe.set_vertex_buffers = nv20_set_vertex_buffers;
nv20->pipe.set_vertex_elements = nv20_set_vertex_elements;
}
src/gallium/drivers/nv20/nv20_state.h
-140
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@@ -1,140 +0,0 @@
#ifndef __NV20_STATE_H__
#define __NV20_STATE_H__
#include "pipe/p_state.h"
#include "tgsi/tgsi_scan.h"
struct nv20_blend_state {
uint32_t b_enable;
uint32_t b_srcfunc;
uint32_t b_dstfunc;
uint32_t c_mask;
uint32_t d_enable;
};
struct nv20_sampler_state {
uint32_t wrap;
uint32_t en;
uint32_t filt;
uint32_t bcol;
};
struct nv20_rasterizer_state {
uint32_t shade_model;
uint32_t line_width;
uint32_t line_smooth_en;
uint32_t point_size;
uint32_t poly_smooth_en;
uint32_t poly_mode_front;
uint32_t poly_mode_back;
uint32_t front_face;
uint32_t cull_face;
uint32_t cull_face_en;
uint32_t point_sprite;
const struct pipe_rasterizer_state *templ;
};
struct nv20_vertex_program_exec {
uint32_t data[4];
boolean has_branch_offset;
int const_index;
};
struct nv20_vertex_program_data {
int index; /* immediates == -1 */
float value[4];
};
struct nv20_vertex_program {
const struct pipe_shader_state *pipe;
boolean translated;
struct nv20_vertex_program_exec *insns;
unsigned nr_insns;
struct nv20_vertex_program_data *consts;
unsigned nr_consts;
struct nouveau_resource *exec;
unsigned exec_start;
struct nouveau_resource *data;
unsigned data_start;
unsigned data_start_min;
uint32_t ir;
uint32_t or;
};
struct nv20_fragment_program_data {
unsigned offset;
unsigned index;
};
struct nv20_fragment_program {
struct pipe_shader_state pipe;
struct tgsi_shader_info info;
boolean translated;
boolean on_hw;
unsigned samplers;
uint32_t *insn;
int insn_len;
struct nv20_fragment_program_data *consts;
unsigned nr_consts;
struct pipe_buffer *buffer;
uint32_t fp_control;
uint32_t fp_reg_control;
};
struct nv20_depth_stencil_alpha_state {
struct {
uint32_t func;
uint32_t write_enable;
uint32_t test_enable;
} depth;
struct {
uint32_t enable;
uint32_t wmask;
uint32_t func;
uint32_t ref;
uint32_t vmask;
uint32_t fail;
uint32_t zfail;
uint32_t zpass;
} stencil;
struct {
uint32_t enabled;
uint32_t func;
uint32_t ref;
} alpha;
};
struct nv20_miptree {
struct pipe_texture base;
struct nouveau_bo *bo;
struct pipe_buffer *buffer;
uint total_size;
struct {
uint pitch;
uint *image_offset;
} level[PIPE_MAX_TEXTURE_LEVELS];
};
#endif
src/gallium/drivers/nv20/nv20_state_emit.c
-426
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@@ -1,426 +0,0 @@
#include "nv20_context.h"
#include "nv20_state.h"
#include "draw/draw_context.h"
static void nv20_state_emit_blend(struct nv20_context* nv20)
{
struct nv20_blend_state *b = nv20->blend;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
BEGIN_RING(chan, kelvin, NV20TCL_DITHER_ENABLE, 1);
OUT_RING (chan, b->d_enable);
BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
OUT_RING (chan, b->b_enable);
BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_SRC, 2);
OUT_RING (chan, b->b_srcfunc);
OUT_RING (chan, b->b_dstfunc);
BEGIN_RING(chan, kelvin, NV20TCL_COLOR_MASK, 1);
OUT_RING (chan, b->c_mask);
}
static void nv20_state_emit_blend_color(struct nv20_context* nv20)
{
struct pipe_blend_color *c = nv20->blend_color;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
BEGIN_RING(chan, kelvin, NV20TCL_BLEND_COLOR, 1);
OUT_RING (chan,
(float_to_ubyte(c->color[3]) << 24)|
(float_to_ubyte(c->color[0]) << 16)|
(float_to_ubyte(c->color[1]) << 8) |
(float_to_ubyte(c->color[2]) << 0));
}
static void nv20_state_emit_rast(struct nv20_context* nv20)
{
struct nv20_rasterizer_state *r = nv20->rast;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
BEGIN_RING(chan, kelvin, NV20TCL_SHADE_MODEL, 2);
OUT_RING (chan, r->shade_model);
OUT_RING (chan, r->line_width);
BEGIN_RING(chan, kelvin, NV20TCL_POINT_SIZE, 1);
OUT_RING (chan, r->point_size);
BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
OUT_RING (chan, r->poly_mode_front);
OUT_RING (chan, r->poly_mode_back);
BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE, 2);
OUT_RING (chan, r->cull_face);
OUT_RING (chan, r->front_face);
BEGIN_RING(chan, kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 2);
OUT_RING (chan, r->line_smooth_en);
OUT_RING (chan, r->poly_smooth_en);
BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
OUT_RING (chan, r->cull_face_en);
}
static void nv20_state_emit_dsa(struct nv20_context* nv20)
{
struct nv20_depth_stencil_alpha_state *d = nv20->dsa;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_FUNC, 1);
OUT_RING (chan, d->depth.func);
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
OUT_RING (chan, d->depth.write_enable);
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
OUT_RING (chan, d->depth.test_enable);
BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_UNK17D8, 1);
OUT_RING (chan, 1);
#if 0
BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_ENABLE, 1);
OUT_RING (chan, d->stencil.enable);
BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_MASK, 7);
OUT_RINGp (chan, (uint32_t *)&(d->stencil.wmask), 7);
#endif
BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
OUT_RING (chan, d->alpha.enabled);
BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_FUNC, 1);
OUT_RING (chan, d->alpha.func);
BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_REF, 1);
OUT_RING (chan, d->alpha.ref);
}
static void nv20_state_emit_viewport(struct nv20_context* nv20)
{
}
static void nv20_state_emit_scissor(struct nv20_context* nv20)
{
/* NV20TCL_SCISSOR_* is probably a software method */
/* struct pipe_scissor_state *s = nv20->scissor;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
BEGIN_RING(chan, kelvin, NV20TCL_SCISSOR_HORIZ, 2);
OUT_RING (chan, ((s->maxx - s->minx) << 16) | s->minx);
OUT_RING (chan, ((s->maxy - s->miny) << 16) | s->miny);*/
}
static void nv20_state_emit_framebuffer(struct nv20_context* nv20)
{
struct pipe_framebuffer_state* fb = nv20->framebuffer;
struct nv04_surface *rt, *zeta = NULL;
uint32_t rt_format, w, h;
int colour_format = 0, zeta_format = 0;
struct nv20_miptree *nv20mt = 0;
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
w = fb->cbufs[0]->width;
h = fb->cbufs[0]->height;
colour_format = fb->cbufs[0]->format;
rt = (struct nv04_surface *)fb->cbufs[0];
if (fb->zsbuf) {
if (colour_format) {
assert(w == fb->zsbuf->width);
assert(h == fb->zsbuf->height);
} else {
w = fb->zsbuf->width;
h = fb->zsbuf->height;
}
zeta_format = fb->zsbuf->format;
zeta = (struct nv04_surface *)fb->zsbuf;
}
rt_format = NV20TCL_RT_FORMAT_TYPE_LINEAR | 0x20;
switch (colour_format) {
case PIPE_FORMAT_X8R8G8B8_UNORM:
rt_format |= NV20TCL_RT_FORMAT_COLOR_X8R8G8B8;
break;
case PIPE_FORMAT_A8R8G8B8_UNORM:
case 0:
rt_format |= NV20TCL_RT_FORMAT_COLOR_A8R8G8B8;
break;
case PIPE_FORMAT_R5G6B5_UNORM:
rt_format |= NV20TCL_RT_FORMAT_COLOR_R5G6B5;
break;
default:
assert(0);
}
if (zeta) {
BEGIN_RING(chan, kelvin, NV20TCL_RT_PITCH, 1);
OUT_RING (chan, rt->pitch | (zeta->pitch << 16));
} else {
BEGIN_RING(chan, kelvin, NV20TCL_RT_PITCH, 1);
OUT_RING (chan, rt->pitch | (rt->pitch << 16));
}
nv20mt = (struct nv20_miptree *)rt->base.texture;
nv20->rt[0] = nv20mt->buffer;
if (zeta_format)
{
nv20mt = (struct nv20_miptree *)zeta->base.texture;
nv20->zeta = nv20mt->buffer;
}
BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 3);
OUT_RING (chan, (w << 16) | 0);
OUT_RING (chan, (h << 16) | 0); /*NV20TCL_RT_VERT */
OUT_RING (chan, rt_format); /* NV20TCL_RT_FORMAT */
BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 2);
OUT_RING (chan, ((w - 1) << 16) | 0);
OUT_RING (chan, ((h - 1) << 16) | 0);
}
static void nv20_vertex_layout(struct nv20_context *nv20)
{
struct nv20_fragment_program *fp = nv20->fragprog.current;
struct draw_context *dc = nv20->draw;
int src;
int i;
struct vertex_info *vinfo = &nv20->vertex_info;
const enum interp_mode colorInterp = INTERP_LINEAR;
boolean colors[2] = { FALSE };
boolean generics[12] = { FALSE };
boolean fog = FALSE;
memset(vinfo, 0, sizeof(*vinfo));
/*
* Assumed NV20 hardware vertex attribute order:
* 0 position, 1 ?, 2 ?, 3 col0,
* 4 col1?, 5 ?, 6 ?, 7 ?,
* 8 ?, 9 tex0, 10 tex1, 11 tex2,
* 12 tex3, 13 ?, 14 ?, 15 ?
* unaccounted: wgh, nor, fog
* There are total 16 attrs.
* vinfo->hwfmt[0] has a used-bit corresponding to each of these.
* relation to TGSI_SEMANTIC_*:
* - POSITION: position (always used)
* - COLOR: col1, col0
* - GENERIC: tex3, tex2, tex1, tex0, normal, weight
* - FOG: fog
*/
for (i = 0; i < fp->info.num_inputs; i++) {
int isn = fp->info.input_semantic_name[i];
int isi = fp->info.input_semantic_index[i];
switch (isn) {
case TGSI_SEMANTIC_POSITION:
break;
case TGSI_SEMANTIC_COLOR:
assert(isi < 2);
colors[isi] = TRUE;
break;
case TGSI_SEMANTIC_GENERIC:
assert(isi < 12);
generics[isi] = TRUE;
break;
case TGSI_SEMANTIC_FOG:
fog = TRUE;
break;
default:
assert(0 && "unknown input_semantic_name");
}
}
/* always do position */ {
src = draw_find_shader_output(dc, TGSI_SEMANTIC_POSITION, 0);
draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_LINEAR, src);
vinfo->hwfmt[0] |= (1 << 0);
}
/* two unnamed generics */
for (i = 4; i < 6; i++) {
if (!generics[i])
continue;
src = draw_find_shader_output(dc, TGSI_SEMANTIC_GENERIC, i);
draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_PERSPECTIVE, src);
vinfo->hwfmt[0] |= (1 << (i - 3));
}
if (colors[0]) {
src = draw_find_shader_output(dc, TGSI_SEMANTIC_COLOR, 0);
draw_emit_vertex_attr(vinfo, EMIT_4F, colorInterp, src);
vinfo->hwfmt[0] |= (1 << 3);
}
if (colors[1]) {
src = draw_find_shader_output(dc, TGSI_SEMANTIC_COLOR, 1);
draw_emit_vertex_attr(vinfo, EMIT_4F, colorInterp, src);
vinfo->hwfmt[0] |= (1 << 4);
}
/* four unnamed generics */
for (i = 6; i < 10; i++) {
if (!generics[i])
continue;
src = draw_find_shader_output(dc, TGSI_SEMANTIC_GENERIC, i);
draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_PERSPECTIVE, src);
vinfo->hwfmt[0] |= (1 << (i - 1));
}
/* tex0, tex1, tex2, tex3 */
for (i = 0; i < 4; i++) {
if (!generics[i])
continue;
src = draw_find_shader_output(dc, TGSI_SEMANTIC_GENERIC, i);
draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_PERSPECTIVE, src);
vinfo->hwfmt[0] |= (1 << (i + 9));
}
/* two unnamed generics */
for (i = 10; i < 12; i++) {
if (!generics[i])
continue;
src = draw_find_shader_output(dc, TGSI_SEMANTIC_GENERIC, i);
draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_PERSPECTIVE, src);
vinfo->hwfmt[0] |= (1 << (i + 3));
}
if (fog) {
src = draw_find_shader_output(dc, TGSI_SEMANTIC_FOG, 0);
draw_emit_vertex_attr(vinfo, EMIT_1F, INTERP_PERSPECTIVE, src);
vinfo->hwfmt[0] |= (1 << 15);
}
draw_compute_vertex_size(vinfo);
}
void
nv20_emit_hw_state(struct nv20_context *nv20)
{
struct nv20_screen *screen = nv20->screen;
struct nouveau_channel *chan = screen->base.channel;
struct nouveau_grobj *kelvin = screen->kelvin;
struct nouveau_bo *rt_bo;
int i;
if (nv20->dirty & NV20_NEW_VERTPROG) {
//nv20_vertprog_bind(nv20, nv20->vertprog.current);
nv20->dirty &= ~NV20_NEW_VERTPROG;
}
if (nv20->dirty & NV20_NEW_FRAGPROG) {
nv20_fragprog_bind(nv20, nv20->fragprog.current);
/*XXX: clear NV20_NEW_FRAGPROG if no new program uploaded */
nv20->dirty_samplers |= (1<<10);
nv20->dirty_samplers = 0;
}
if (nv20->dirty_samplers || (nv20->dirty & NV20_NEW_FRAGPROG)) {
nv20_fragtex_bind(nv20);
nv20->dirty &= ~NV20_NEW_FRAGPROG;
}
if (nv20->dirty & NV20_NEW_VTXARRAYS) {
nv20->dirty &= ~NV20_NEW_VTXARRAYS;
nv20_vertex_layout(nv20);
nv20_vtxbuf_bind(nv20);
}
if (nv20->dirty & NV20_NEW_BLEND) {
nv20->dirty &= ~NV20_NEW_BLEND;
nv20_state_emit_blend(nv20);
}
if (nv20->dirty & NV20_NEW_BLENDCOL) {
nv20->dirty &= ~NV20_NEW_BLENDCOL;
nv20_state_emit_blend_color(nv20);
}
if (nv20->dirty & NV20_NEW_RAST) {
nv20->dirty &= ~NV20_NEW_RAST;
nv20_state_emit_rast(nv20);
}
if (nv20->dirty & NV20_NEW_DSA) {
nv20->dirty &= ~NV20_NEW_DSA;
nv20_state_emit_dsa(nv20);
}
if (nv20->dirty & NV20_NEW_VIEWPORT) {
nv20->dirty &= ~NV20_NEW_VIEWPORT;
nv20_state_emit_viewport(nv20);
}
if (nv20->dirty & NV20_NEW_SCISSOR) {
nv20->dirty &= ~NV20_NEW_SCISSOR;
nv20_state_emit_scissor(nv20);
}
if (nv20->dirty & NV20_NEW_FRAMEBUFFER) {
nv20->dirty &= ~NV20_NEW_FRAMEBUFFER;
nv20_state_emit_framebuffer(nv20);
}
/* Emit relocs for every referenced buffer.
* This is to ensure the bufmgr has an accurate idea of how
* the buffer is used. This isn't very efficient, but we don't
* seem to take a significant performance hit. Will be improved
* at some point. Vertex arrays are emitted by nv20_vbo.c
*/
/* Render target */
rt_bo = nouveau_bo(nv20->rt[0]);
BEGIN_RING(chan, kelvin, NV20TCL_DMA_COLOR, 1);
OUT_RELOCo(chan, rt_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(chan, kelvin, NV20TCL_COLOR_OFFSET, 1);
OUT_RELOCl(chan, rt_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
if (nv20->zeta) {
struct nouveau_bo *zeta_bo = nouveau_bo(nv20->zeta);
BEGIN_RING(chan, kelvin, NV20TCL_DMA_ZETA, 1);
OUT_RELOCo(chan, zeta_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(chan, kelvin, NV20TCL_ZETA_OFFSET, 1);
OUT_RELOCl(chan, zeta_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
/* XXX for when we allocate LMA on nv17 */
/* BEGIN_RING(chan, kelvin, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1);
OUT_RELOCl(chan, nouveau_bo(nv20->zeta + lma_offset));*/
}
/* Vertex buffer */
BEGIN_RING(chan, kelvin, NV20TCL_DMA_VTXBUF0, 1);
OUT_RELOCo(chan, rt_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(chan, kelvin, NV20TCL_COLOR_OFFSET, 1);
OUT_RELOCl(chan, rt_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
/* Texture images */
for (i = 0; i < 2; i++) {
if (!(nv20->fp_samplers & (1 << i)))
continue;
struct nouveau_bo *bo = nouveau_bo(nv20->tex[i].buffer);
BEGIN_RING(chan, kelvin, NV20TCL_TX_OFFSET(i), 1);
OUT_RELOCl(chan, bo, 0, NOUVEAU_BO_VRAM |
NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_RING(chan, kelvin, NV20TCL_TX_FORMAT(i), 1);
OUT_RELOCd(chan, bo, nv20->tex[i].format,
NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
NOUVEAU_BO_OR, NV20TCL_TX_FORMAT_DMA0,
NV20TCL_TX_FORMAT_DMA1);
}
}
src/gallium/drivers/nv20/nv20_surface.c
-63
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@@ -1,63 +0,0 @@
/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#include "nv20_context.h"
#include "pipe/p_defines.h"
#include "util/u_simple_screen.h"
#include "util/u_inlines.h"
#include "util/u_tile.h"
static void
nv20_surface_copy(struct pipe_context *pipe,
struct pipe_surface *dest, unsigned destx, unsigned desty,
struct pipe_surface *src, unsigned srcx, unsigned srcy,
unsigned width, unsigned height)
{
struct nv20_context *nv20 = nv20_context(pipe);
struct nv04_surface_2d *eng2d = nv20->screen->eng2d;
eng2d->copy(eng2d, dest, destx, desty, src, srcx, srcy, width, height);
}
static void
nv20_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest,
unsigned destx, unsigned desty, unsigned width,
unsigned height, unsigned value)
{
struct nv20_context *nv20 = nv20_context(pipe);
struct nv04_surface_2d *eng2d = nv20->screen->eng2d;
eng2d->fill(eng2d, dest, destx, desty, width, height, value);
}
void
nv20_init_surface_functions(struct nv20_context *nv20)
{
nv20->pipe.surface_copy = nv20_surface_copy;
nv20->pipe.surface_fill = nv20_surface_fill;
}
src/gallium/drivers/nv20/nv20_transfer.c
-178
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@@ -1,178 +0,0 @@
#include <pipe/p_state.h>
#include <pipe/p_defines.h>
#include <util/u_inlines.h>
#include <util/u_format.h>
#include <util/u_memory.h>
#include <util/u_math.h>
#include <nouveau/nouveau_winsys.h>
#include "nv20_context.h"
#include "nv20_screen.h"
#include "nv20_state.h"
struct nv20_transfer {
struct pipe_transfer base;
struct pipe_surface *surface;
boolean direct;
};
static void
nv20_compatible_transfer_tex(struct pipe_texture *pt, unsigned width, unsigned height,
struct pipe_texture *template)
{
memset(template, 0, sizeof(struct pipe_texture));
template->target = pt->target;
template->format = pt->format;
template->width0 = width;
template->height0 = height;
template->depth0 = 1;
template->last_level = 0;
template->nr_samples = pt->nr_samples;
template->tex_usage = PIPE_TEXTURE_USAGE_DYNAMIC |
NOUVEAU_TEXTURE_USAGE_LINEAR;
}
static struct pipe_transfer *
nv20_transfer_new(struct pipe_screen *pscreen, struct pipe_texture *pt,
unsigned face, unsigned level, unsigned zslice,
enum pipe_transfer_usage usage,
unsigned x, unsigned y, unsigned w, unsigned h)
{
struct nv20_miptree *mt = (struct nv20_miptree *)pt;
struct nv20_transfer *tx;
struct pipe_texture tx_tex_template, *tx_tex;
tx = CALLOC_STRUCT(nv20_transfer);
if (!tx)
return NULL;
pipe_texture_reference(&tx->base.texture, pt);
tx->base.x = x;
tx->base.y = y;
tx->base.width = w;
tx->base.height = h;
tx->base.stride = mt->level[level].pitch;
tx->base.usage = usage;
tx->base.face = face;
tx->base.level = level;
tx->base.zslice = zslice;
/* Direct access to texture */
if ((pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC ||
debug_get_bool_option("NOUVEAU_NO_TRANSFER", TRUE/*XXX:FALSE*/)) &&
pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)
{
tx->direct = true;
tx->surface = pscreen->get_tex_surface(pscreen, pt,
0, 0, 0,
pipe_transfer_buffer_flags(&tx->base));
return &tx->base;
}
tx->direct = false;
nv20_compatible_transfer_tex(pt, w, h, &tx_tex_template);
tx_tex = pscreen->texture_create(pscreen, &tx_tex_template);
if (!tx_tex)
{
FREE(tx);
return NULL;
}
tx->base.stride = ((struct nv20_miptree*)tx_tex)->level[0].pitch;
tx->surface = pscreen->get_tex_surface(pscreen, tx_tex,
face, level, zslice,
pipe_transfer_buffer_flags(&tx->base));
pipe_texture_reference(&tx_tex, NULL);
if (!tx->surface)
{
pipe_surface_reference(&tx->surface, NULL);
FREE(tx);
return NULL;
}
if (usage & PIPE_TRANSFER_READ) {
struct nv20_screen *nvscreen = nv20_screen(pscreen);
struct pipe_surface *src;
src = pscreen->get_tex_surface(pscreen, pt,
face, level, zslice,
PIPE_BUFFER_USAGE_GPU_READ);
/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
/* TODO: Check if SIFM can un-swizzle */
nvscreen->eng2d->copy(nvscreen->eng2d,
tx->surface, 0, 0,
src, x, y,
w, h);
pipe_surface_reference(&src, NULL);
}
return &tx->base;
}
static void
nv20_transfer_del(struct pipe_transfer *ptx)
{
struct nv20_transfer *tx = (struct nv20_transfer *)ptx;
if (!tx->direct && (ptx->usage = PIPE_TRANSFER_WRITE)) {
struct pipe_screen *pscreen = ptx->texture->screen;
struct nv20_screen *nvscreen = nv20_screen(pscreen);
struct pipe_surface *dst;
dst = pscreen->get_tex_surface(pscreen, ptx->texture,
ptx->face, ptx->level, ptx->zslice,
PIPE_BUFFER_USAGE_GPU_WRITE | NOUVEAU_BUFFER_USAGE_NO_RENDER);
/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
nvscreen->eng2d->copy(nvscreen->eng2d,
dst, tx->base.x, tx->base.y,
tx->surface, 0, 0,
tx->base.width, tx->base.height);
pipe_surface_reference(&dst, NULL);
}
pipe_surface_reference(&tx->surface, NULL);
pipe_texture_reference(&ptx->texture, NULL);
FREE(ptx);
}
static void *
nv20_transfer_map(struct pipe_screen *pscreen, struct pipe_transfer *ptx)
{
struct nv20_transfer *tx = (struct nv20_transfer *)ptx;
struct nv04_surface *ns = (struct nv04_surface *)tx->surface;
struct nv20_miptree *mt = (struct nv20_miptree *)tx->surface->texture;
void *map = pipe_buffer_map(pscreen, mt->buffer,
pipe_transfer_buffer_flags(ptx));
if(!tx->direct)
return map + ns->base.offset;
else
return map + ns->base.offset + ptx->y * ns->pitch + ptx->x * util_format_get_blocksize(ptx->texture->format);
}
static void
nv20_transfer_unmap(struct pipe_screen *pscreen, struct pipe_transfer *ptx)
{
struct nv20_transfer *tx = (struct nv20_transfer *)ptx;
struct nv20_miptree *mt = (struct nv20_miptree *)tx->surface->texture;
pipe_buffer_unmap(pscreen, mt->buffer);
}
void
nv20_screen_init_transfer_functions(struct pipe_screen *pscreen)
{
pscreen->get_tex_transfer = nv20_transfer_new;
pscreen->tex_transfer_destroy = nv20_transfer_del;
pscreen->transfer_map = nv20_transfer_map;
pscreen->transfer_unmap = nv20_transfer_unmap;
}
src/gallium/drivers/nv20/nv20_vbo.c
-79
View File
@@ -1,79 +0,0 @@
#include "draw/draw_context.h"
#include "pipe/p_context.h"
#include "pipe/p_state.h"
#include "util/u_inlines.h"
#include "nv20_context.h"
#include "nv20_state.h"
#include "nouveau/nouveau_channel.h"
#include "nouveau/nouveau_pushbuf.h"
void nv20_draw_elements( struct pipe_context *pipe,
struct pipe_buffer *indexBuffer,
unsigned indexSize,
unsigned prim, unsigned start, unsigned count)
{
struct pipe_screen *pscreen = pipe->screen;
struct nv20_context *nv20 = nv20_context( pipe );
struct draw_context *draw = nv20->draw;
unsigned i;
nv20_emit_hw_state(nv20);
/*
* Map vertex buffers
*/
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (nv20->vtxbuf[i].buffer) {
void *buf
= pipe_buffer_map(pscreen,
nv20->vtxbuf[i].buffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_vertex_buffer(draw, i, buf);
}
}
/* Map index buffer, if present */
if (indexBuffer) {
void *mapped_indexes
= pipe_buffer_map(pscreen, indexBuffer,
PIPE_BUFFER_USAGE_CPU_READ);
draw_set_mapped_element_buffer(draw, indexSize, mapped_indexes);
}
else {
/* no index/element buffer */
draw_set_mapped_element_buffer(draw, 0, NULL);
}
draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0,
nv20->constbuf[PIPE_SHADER_VERTEX],
nv20->constbuf_nr[PIPE_SHADER_VERTEX]);
/* draw! */
draw_arrays(nv20->draw, prim, start, count);
/*
* unmap vertex/index buffers
*/
for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
if (nv20->vtxbuf[i].buffer) {
pipe_buffer_unmap(pscreen, nv20->vtxbuf[i].buffer);
draw_set_mapped_vertex_buffer(draw, i, NULL);
}
}
if (indexBuffer) {
pipe_buffer_unmap(pscreen, indexBuffer);
draw_set_mapped_element_buffer(draw, 0, NULL);
}
draw_flush(nv20->draw);
}
void nv20_draw_arrays( struct pipe_context *pipe,
unsigned prim, unsigned start, unsigned count)
{
nv20_draw_elements(pipe, NULL, 0, prim, start, count);
}
src/gallium/drivers/nv20/nv20_vertprog.c
-841
View File
@@ -1,841 +0,0 @@
#include "pipe/p_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "util/u_inlines.h"
#include "pipe/p_shader_tokens.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_dump.h"
#include "nv20_context.h"
#include "nv20_state.h"
/* TODO (at least...):
* 1. Indexed consts + ARL
* 2. Arb. swz/negation
* 3. NV_vp11, NV_vp2, NV_vp3 features
* - extra arith opcodes
* - branching
* - texture sampling
* - indexed attribs
* - indexed results
* 4. bugs
*/
#define SWZ_X 0
#define SWZ_Y 1
#define SWZ_Z 2
#define SWZ_W 3
#define MASK_X 8
#define MASK_Y 4
#define MASK_Z 2
#define MASK_W 1
#define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
#define DEF_SCALE 0
#define DEF_CTEST 0
#include "nv20_shader.h"
#define swz(s,x,y,z,w) nv20_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
#define neg(s) nv20_sr_neg((s))
#define abs(s) nv20_sr_abs((s))
struct nv20_vpc {
struct nv20_vertex_program *vp;
struct nv20_vertex_program_exec *vpi;
unsigned output_map[PIPE_MAX_SHADER_OUTPUTS];
int high_temp;
int temp_temp_count;
struct nv20_sreg *imm;
unsigned nr_imm;
};
static struct nv20_sreg
temp(struct nv20_vpc *vpc)
{
int idx;
idx = vpc->temp_temp_count++;
idx += vpc->high_temp + 1;
return nv20_sr(NV30SR_TEMP, idx);
}
static struct nv20_sreg
constant(struct nv20_vpc *vpc, int pipe, float x, float y, float z, float w)
{
struct nv20_vertex_program *vp = vpc->vp;
struct nv20_vertex_program_data *vpd;
int idx;
if (pipe >= 0) {
for (idx = 0; idx < vp->nr_consts; idx++) {
if (vp->consts[idx].index == pipe)
return nv20_sr(NV30SR_CONST, idx);
}
}
idx = vp->nr_consts++;
vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
vpd = &vp->consts[idx];
vpd->index = pipe;
vpd->value[0] = x;
vpd->value[1] = y;
vpd->value[2] = z;
vpd->value[3] = w;
return nv20_sr(NV30SR_CONST, idx);
}
#define arith(cc,s,o,d,m,s0,s1,s2) \
nv20_vp_arith((cc), (s), NV30_VP_INST_##o, (d), (m), (s0), (s1), (s2))
static void
emit_src(struct nv20_vpc *vpc, uint32_t *hw, int pos, struct nv20_sreg src)
{
struct nv20_vertex_program *vp = vpc->vp;
uint32_t sr = 0;
switch (src.type) {
case NV30SR_TEMP:
sr |= (NV30_VP_SRC_REG_TYPE_TEMP << NV30_VP_SRC_REG_TYPE_SHIFT);
sr |= (src.index << NV30_VP_SRC_TEMP_SRC_SHIFT);
break;
case NV30SR_INPUT:
sr |= (NV30_VP_SRC_REG_TYPE_INPUT <<
NV30_VP_SRC_REG_TYPE_SHIFT);
vp->ir |= (1 << src.index);
hw[1] |= (src.index << NV30_VP_INST_INPUT_SRC_SHIFT);
break;
case NV30SR_CONST:
sr |= (NV30_VP_SRC_REG_TYPE_CONST <<
NV30_VP_SRC_REG_TYPE_SHIFT);
assert(vpc->vpi->const_index == -1 ||
vpc->vpi->const_index == src.index);
vpc->vpi->const_index = src.index;
break;
case NV30SR_NONE:
sr |= (NV30_VP_SRC_REG_TYPE_INPUT <<
NV30_VP_SRC_REG_TYPE_SHIFT);
break;
default:
assert(0);
}
if (src.negate)
sr |= NV30_VP_SRC_NEGATE;
if (src.abs)
hw[0] |= (1 << (21 + pos));
sr |= ((src.swz[0] << NV30_VP_SRC_SWZ_X_SHIFT) |
(src.swz[1] << NV30_VP_SRC_SWZ_Y_SHIFT) |
(src.swz[2] << NV30_VP_SRC_SWZ_Z_SHIFT) |
(src.swz[3] << NV30_VP_SRC_SWZ_W_SHIFT));
/*
* |VVV|
* d�.�b
* \u/
*
*/
switch (pos) {
case 0:
hw[1] |= ((sr & NV30_VP_SRC0_HIGH_MASK) >>
NV30_VP_SRC0_HIGH_SHIFT) << NV30_VP_INST_SRC0H_SHIFT;
hw[2] |= (sr & NV30_VP_SRC0_LOW_MASK) <<
NV30_VP_INST_SRC0L_SHIFT;
break;
case 1:
hw[2] |= sr << NV30_VP_INST_SRC1_SHIFT;
break;
case 2:
hw[2] |= ((sr & NV30_VP_SRC2_HIGH_MASK) >>
NV30_VP_SRC2_HIGH_SHIFT) << NV30_VP_INST_SRC2H_SHIFT;
hw[3] |= (sr & NV30_VP_SRC2_LOW_MASK) <<
NV30_VP_INST_SRC2L_SHIFT;
break;
default:
assert(0);
}
}
static void
emit_dst(struct nv20_vpc *vpc, uint32_t *hw, int slot, struct nv20_sreg dst)
{
struct nv20_vertex_program *vp = vpc->vp;
switch (dst.type) {
case NV30SR_TEMP:
hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
break;
case NV30SR_OUTPUT:
switch (dst.index) {
case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
case NV30_VP_INST_DEST_FOGC : vp->or |= (1 << 4); break;
case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
default:
break;
}
hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
/*XXX: no way this is entirely correct, someone needs to
* figure out what exactly it is.
*/
hw[3] |= 0x800;
break;
default:
assert(0);
}
}
static void
nv20_vp_arith(struct nv20_vpc *vpc, int slot, int op,
struct nv20_sreg dst, int mask,
struct nv20_sreg s0, struct nv20_sreg s1,
struct nv20_sreg s2)
{
struct nv20_vertex_program *vp = vpc->vp;
uint32_t *hw;
vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
vpc->vpi = &vp->insns[vp->nr_insns - 1];
memset(vpc->vpi, 0, sizeof(*vpc->vpi));
vpc->vpi->const_index = -1;
hw = vpc->vpi->data;
hw[0] |= (NV30_VP_INST_COND_TR << NV30_VP_INST_COND_SHIFT);
hw[0] |= ((0 << NV30_VP_INST_COND_SWZ_X_SHIFT) |
(1 << NV30_VP_INST_COND_SWZ_Y_SHIFT) |
(2 << NV30_VP_INST_COND_SWZ_Z_SHIFT) |
(3 << NV30_VP_INST_COND_SWZ_W_SHIFT));
hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
// hw[3] |= NV30_VP_INST_SCA_DEST_TEMP_MASK;
// hw[3] |= (mask << NV30_VP_INST_VEC_WRITEMASK_SHIFT);
if (dst.type == NV30SR_OUTPUT) {
if (slot)
hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
else
hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
} else {
if (slot)
hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
else
hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
}
emit_dst(vpc, hw, slot, dst);
emit_src(vpc, hw, 0, s0);
emit_src(vpc, hw, 1, s1);
emit_src(vpc, hw, 2, s2);
}
static INLINE struct nv20_sreg
tgsi_src(struct nv20_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
struct nv20_sreg src;
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
src = nv20_sr(NV30SR_INPUT, fsrc->Register.Index);
break;
case TGSI_FILE_CONSTANT:
src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
break;
case TGSI_FILE_IMMEDIATE:
src = vpc->imm[fsrc->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
if (vpc->high_temp < fsrc->Register.Index)
vpc->high_temp = fsrc->Register.Index;
src = nv20_sr(NV30SR_TEMP, fsrc->Register.Index);
break;
default:
NOUVEAU_ERR("bad src file\n");
break;
}
src.abs = fsrc->Register.Absolute;
src.negate = fsrc->Register.Negate;
src.swz[0] = fsrc->Register.SwizzleX;
src.swz[1] = fsrc->Register.SwizzleY;
src.swz[2] = fsrc->Register.SwizzleZ;
src.swz[3] = fsrc->Register.SwizzleW;
return src;
}
static INLINE struct nv20_sreg
tgsi_dst(struct nv20_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv20_sreg dst;
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = nv20_sr(NV30SR_OUTPUT,
vpc->output_map[fdst->Register.Index]);
break;
case TGSI_FILE_TEMPORARY:
dst = nv20_sr(NV30SR_TEMP, fdst->Register.Index);
if (vpc->high_temp < dst.index)
vpc->high_temp = dst.index;
break;
default:
NOUVEAU_ERR("bad dst file\n");
break;
}
return dst;
}
static INLINE int
tgsi_mask(uint tgsi)
{
int mask = 0;
if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
return mask;
}
static boolean
nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
const struct tgsi_full_instruction *finst)
{
struct nv20_sreg src[3], dst, tmp;
struct nv20_sreg none = nv20_sr(NV30SR_NONE, 0);
int mask;
int ai = -1, ci = -1;
int i;
if (finst->Instruction.Opcode == TGSI_OPCODE_END)
return TRUE;
vpc->temp_temp_count = 0;
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->Src[i];
if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
}
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
fsrc = &finst->Src[i];
switch (fsrc->Register.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->Register.Index) {
ai = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
tgsi_src(vpc, fsrc), none, none);
}
break;
/*XXX: index comparison is broken now that consts come from
* two different register files.
*/
case TGSI_FILE_CONSTANT:
case TGSI_FILE_IMMEDIATE:
if (ci == -1 || ci == fsrc->Register.Index) {
ci = fsrc->Register.Index;
src[i] = tgsi_src(vpc, fsrc);
} else {
src[i] = temp(vpc);
arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
tgsi_src(vpc, fsrc), none, none);
}
break;
case TGSI_FILE_TEMPORARY:
/* handled above */
break;
default:
NOUVEAU_ERR("bad src file\n");
return FALSE;
}
}
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
arith(vpc, 0, OP_MOV, dst, mask, abs(src[0]), none, none);
break;
case TGSI_OPCODE_ADD:
arith(vpc, 0, OP_ADD, dst, mask, src[0], none, src[1]);
break;
case TGSI_OPCODE_ARL:
arith(vpc, 0, OP_ARL, dst, mask, src[0], none, none);
break;
case TGSI_OPCODE_DP3:
arith(vpc, 0, OP_DP3, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_DP4:
arith(vpc, 0, OP_DP4, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_DPH:
arith(vpc, 0, OP_DPH, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_DST:
arith(vpc, 0, OP_DST, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_EX2:
arith(vpc, 1, OP_EX2, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_EXP:
arith(vpc, 1, OP_EXP, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_FLR:
arith(vpc, 0, OP_FLR, dst, mask, src[0], none, none);
break;
case TGSI_OPCODE_FRC:
arith(vpc, 0, OP_FRC, dst, mask, src[0], none, none);
break;
case TGSI_OPCODE_LG2:
arith(vpc, 1, OP_LG2, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_LIT:
arith(vpc, 1, OP_LIT, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_LOG:
arith(vpc, 1, OP_LOG, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_MAD:
arith(vpc, 0, OP_MAD, dst, mask, src[0], src[1], src[2]);
break;
case TGSI_OPCODE_MAX:
arith(vpc, 0, OP_MAX, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_MIN:
arith(vpc, 0, OP_MIN, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_MOV:
arith(vpc, 0, OP_MOV, dst, mask, src[0], none, none);
break;
case TGSI_OPCODE_MUL:
arith(vpc, 0, OP_MUL, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_POW:
tmp = temp(vpc);
arith(vpc, 1, OP_LG2, tmp, MASK_X, none, none,
swz(src[0], X, X, X, X));
arith(vpc, 0, OP_MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
swz(src[1], X, X, X, X), none);
arith(vpc, 1, OP_EX2, dst, mask, none, none,
swz(tmp, X, X, X, X));
break;
case TGSI_OPCODE_RCP:
arith(vpc, 1, OP_RCP, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_RET:
break;
case TGSI_OPCODE_RSQ:
arith(vpc, 1, OP_RSQ, dst, mask, none, none, src[0]);
break;
case TGSI_OPCODE_SGE:
arith(vpc, 0, OP_SGE, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_SGT:
arith(vpc, 0, OP_SGT, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_SLT:
arith(vpc, 0, OP_SLT, dst, mask, src[0], src[1], none);
break;
case TGSI_OPCODE_SUB:
arith(vpc, 0, OP_ADD, dst, mask, src[0], none, neg(src[1]));
break;
case TGSI_OPCODE_XPD:
tmp = temp(vpc);
arith(vpc, 0, OP_MUL, tmp, mask,
swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
arith(vpc, 0, OP_MAD, dst, (mask & ~MASK_W),
swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
neg(tmp));
break;
default:
NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
return FALSE;
}
return TRUE;
}
static boolean
nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc,
const struct tgsi_full_declaration *fdec)
{
int hw;
switch (fdec->Semantic.Name) {
case TGSI_SEMANTIC_POSITION:
hw = NV30_VP_INST_DEST_POS;
break;
case TGSI_SEMANTIC_COLOR:
if (fdec->Semantic.Index == 0) {
hw = NV30_VP_INST_DEST_COL0;
} else
if (fdec->Semantic.Index == 1) {
hw = NV30_VP_INST_DEST_COL1;
} else {
NOUVEAU_ERR("bad colour semantic index\n");
return FALSE;
}
break;
case TGSI_SEMANTIC_BCOLOR:
if (fdec->Semantic.Index == 0) {
hw = NV30_VP_INST_DEST_BFC0;
} else
if (fdec->Semantic.Index == 1) {
hw = NV30_VP_INST_DEST_BFC1;
} else {
NOUVEAU_ERR("bad bcolour semantic index\n");
return FALSE;
}
break;
case TGSI_SEMANTIC_FOG:
hw = NV30_VP_INST_DEST_FOGC;
break;
case TGSI_SEMANTIC_PSIZE:
hw = NV30_VP_INST_DEST_PSZ;
break;
case TGSI_SEMANTIC_GENERIC:
if (fdec->Semantic.Index <= 7) {
hw = NV30_VP_INST_DEST_TC(fdec->Semantic.Index);
} else {
NOUVEAU_ERR("bad generic semantic index\n");
return FALSE;
}
break;
case TGSI_SEMANTIC_EDGEFLAG:
NOUVEAU_ERR("cannot handle edgeflag output\n");
return FALSE;
default:
NOUVEAU_ERR("bad output semantic\n");
return FALSE;
}
vpc->output_map[fdec->Range.First] = hw;
return TRUE;
}
static boolean
nv20_vertprog_prepare(struct nv20_vpc *vpc)
{
struct tgsi_parse_context p;
int nr_imm = 0;
tgsi_parse_init(&p, vpc->vp->pipe.tokens);
while (!tgsi_parse_end_of_tokens(&p)) {
const union tgsi_full_token *tok = &p.FullToken;
tgsi_parse_token(&p);
switch(tok->Token.Type) {
case TGSI_TOKEN_TYPE_IMMEDIATE:
nr_imm++;
break;
default:
break;
}
}
tgsi_parse_free(&p);
if (nr_imm) {
vpc->imm = CALLOC(nr_imm, sizeof(struct nv20_sreg));
assert(vpc->imm);
}
return TRUE;
}
static void
nv20_vertprog_translate(struct nv20_context *nv20,
struct nv20_vertex_program *vp)
{
struct tgsi_parse_context parse;
struct nv20_vpc *vpc = NULL;
tgsi_dump(vp->pipe.tokens,0);
vpc = CALLOC(1, sizeof(struct nv20_vpc));
if (!vpc)
return;
vpc->vp = vp;
vpc->high_temp = -1;
if (!nv20_vertprog_prepare(vpc)) {
FREE(vpc);
return;
}
tgsi_parse_init(&parse, vp->pipe.tokens);
while (!tgsi_parse_end_of_tokens(&parse)) {
tgsi_parse_token(&parse);
switch (parse.FullToken.Token.Type) {
case TGSI_TOKEN_TYPE_DECLARATION:
{
const struct tgsi_full_declaration *fdec;
fdec = &parse.FullToken.FullDeclaration;
switch (fdec->Declaration.File) {
case TGSI_FILE_OUTPUT:
if (!nv20_vertprog_parse_decl_output(vpc, fdec))
goto out_err;
break;
default:
break;
}
}
break;
case TGSI_TOKEN_TYPE_IMMEDIATE:
{
const struct tgsi_full_immediate *imm;
imm = &parse.FullToken.FullImmediate;
assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
assert(imm->Immediate.NrTokens == 4 + 1);
vpc->imm[vpc->nr_imm++] =
constant(vpc, -1,
imm->u[0].Float,
imm->u[1].Float,
imm->u[2].Float,
imm->u[3].Float);
}
break;
case TGSI_TOKEN_TYPE_INSTRUCTION:
{
const struct tgsi_full_instruction *finst;
finst = &parse.FullToken.FullInstruction;
if (!nv20_vertprog_parse_instruction(vpc, finst))
goto out_err;
}
break;
default:
break;
}
}
vp->insns[vp->nr_insns - 1].data[3] |= NV30_VP_INST_LAST;
vp->translated = TRUE;
out_err:
tgsi_parse_free(&parse);
FREE(vpc);
}
static boolean
nv20_vertprog_validate(struct nv20_context *nv20)
{
struct pipe_screen *pscreen = nv20->pipe.screen;
struct nouveau_winsys *nvws = nv20->nvws;
struct nouveau_grobj *rankine = nv20->screen->rankine;
struct nv20_vertex_program *vp;
struct pipe_buffer *constbuf;
boolean upload_code = FALSE, upload_data = FALSE;
int i;
vp = nv20->vertprog;
constbuf = nv20->constbuf[PIPE_SHADER_VERTEX];
/* Translate TGSI shader into hw bytecode */
if (!vp->translated) {
nv20_vertprog_translate(nv20, vp);
if (!vp->translated)
return FALSE;
}
/* Allocate hw vtxprog exec slots */
if (!vp->exec) {
struct nouveau_resource *heap = nv20->screen->vp_exec_heap;
struct nouveau_stateobj *so;
uint vplen = vp->nr_insns;
if (nvws->res_alloc(heap, vplen, vp, &vp->exec)) {
while (heap->next && heap->size < vplen) {
struct nv20_vertex_program *evict;
evict = heap->next->priv;
nvws->res_free(&evict->exec);
}
if (nvws->res_alloc(heap, vplen, vp, &vp->exec))
assert(0);
}
so = so_new(2, 0);
so_method(so, rankine, NV34TCL_VP_START_FROM_ID, 1);
so_data (so, vp->exec->start);
so_ref(so, &vp->so);
upload_code = TRUE;
}
/* Allocate hw vtxprog const slots */
if (vp->nr_consts && !vp->data) {
struct nouveau_resource *heap = nv20->screen->vp_data_heap;
if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data)) {
while (heap->next && heap->size < vp->nr_consts) {
struct nv20_vertex_program *evict;
evict = heap->next->priv;
nvws->res_free(&evict->data);
}
if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data))
assert(0);
}
/*XXX: handle this some day */
assert(vp->data->start >= vp->data_start_min);
upload_data = TRUE;
if (vp->data_start != vp->data->start)
upload_code = TRUE;
}
/* If exec or data segments moved we need to patch the program to
* fixup offsets and register IDs.
*/
if (vp->exec_start != vp->exec->start) {
for (i = 0; i < vp->nr_insns; i++) {
struct nv20_vertex_program_exec *vpi = &vp->insns[i];
if (vpi->has_branch_offset) {
assert(0);
}
}
vp->exec_start = vp->exec->start;
}
if (vp->nr_consts && vp->data_start != vp->data->start) {
for (i = 0; i < vp->nr_insns; i++) {
struct nv20_vertex_program_exec *vpi = &vp->insns[i];
if (vpi->const_index >= 0) {
vpi->data[1] &= ~NV30_VP_INST_CONST_SRC_MASK;
vpi->data[1] |=
(vpi->const_index + vp->data->start) <<
NV30_VP_INST_CONST_SRC_SHIFT;
}
}
vp->data_start = vp->data->start;
}
/* Update + Upload constant values */
if (vp->nr_consts) {
float *map = NULL;
if (constbuf) {
map = pipe_buffer_map(pscreen, constbuf,
PIPE_BUFFER_USAGE_CPU_READ);
}
for (i = 0; i < vp->nr_consts; i++) {
struct nv20_vertex_program_data *vpd = &vp->consts[i];
if (vpd->index >= 0) {
if (!upload_data &&
!memcmp(vpd->value, &map[vpd->index * 4],
4 * sizeof(float)))
continue;
memcpy(vpd->value, &map[vpd->index * 4],
4 * sizeof(float));
}
BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_CONST_ID, 5);
OUT_RING (i + vp->data->start);
OUT_RINGp ((uint32_t *)vpd->value, 4);
}
if (constbuf)
pipe_buffer_unmap(pscreen, constbuf);
}
/* Upload vtxprog */
if (upload_code) {
#if 0
for (i = 0; i < vp->nr_insns; i++) {
NOUVEAU_MSG("VP inst %d: 0x%08x 0x%08x 0x%08x 0x%08x\n",
i, vp->insns[i].data[0], vp->insns[i].data[1],
vp->insns[i].data[2], vp->insns[i].data[3]);
}
#endif
BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_FROM_ID, 1);
OUT_RING (vp->exec->start);
for (i = 0; i < vp->nr_insns; i++) {
BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_INST(0), 4);
OUT_RINGp (vp->insns[i].data, 4);
}
}
if (vp->so != nv20->state.hw[NV30_STATE_VERTPROG]) {
so_ref(vp->so, &nv20->state.hw[NV30_STATE_VERTPROG]);
return TRUE;
}
return FALSE;
}
void
nv20_vertprog_destroy(struct nv20_context *nv20, struct nv20_vertex_program *vp)
{
struct nouveau_winsys *nvws = nv20->screen->nvws;
vp->translated = FALSE;
if (vp->nr_insns) {
FREE(vp->insns);
vp->insns = NULL;
vp->nr_insns = 0;
}
if (vp->nr_consts) {
FREE(vp->consts);
vp->consts = NULL;
vp->nr_consts = 0;
}
nvws->res_free(&vp->exec);
vp->exec_start = 0;
nvws->res_free(&vp->data);
vp->data_start = 0;
vp->data_start_min = 0;
vp->ir = vp->or = 0;
so_ref(NULL, &vp->so);
}
struct nv20_state_entry nv20_state_vertprog = {
.validate = nv20_vertprog_validate,
.dirty = {
.pipe = NV30_NEW_VERTPROG /*| NV30_NEW_UCP*/,
.hw = NV30_STATE_VERTPROG,
}
};
src/gallium/drivers/nv30/nv30_miptree.c
+1 -1
View File
@@ -5,7 +5,7 @@
#include "util/u_math.h"
#include "nv30_context.h"
#include "../nv04/nv04_surface_2d.h"
#include "../nouveau/nv04_surface_2d.h"
static void
nv30_miptree_layout(struct nv30_miptree *nv30mt)
src/gallium/drivers/nv30/nv30_screen.h
+1 -1
View File
@@ -3,7 +3,7 @@
#include "nouveau/nouveau_screen.h"
#include "nv04/nv04_surface_2d.h"
#include "nouveau/nv04_surface_2d.h"
struct nv30_screen {
struct nouveau_screen base;
src/gallium/drivers/nv40/nv40_miptree.c
+1 -1
View File
@@ -5,7 +5,7 @@
#include "util/u_math.h"
#include "nv40_context.h"
#include "../nv04/nv04_surface_2d.h"
#include "../nouveau/nv04_surface_2d.h"
src/gallium/drivers/nv40/nv40_screen.h
+1 -1
View File
@@ -2,7 +2,7 @@
#define __NV40_SCREEN_H__
#include "nouveau/nouveau_screen.h"
#include "nv04/nv04_surface_2d.h"
#include "nouveau/nv04_surface_2d.h"
struct nv40_screen {
struct nouveau_screen base;
src/gallium/winsys/drm/nouveau/dri/Makefile
-3
View File
@@ -6,9 +6,6 @@ LIBNAME = nouveau_dri.so
PIPE_DRIVERS = \
$(TOP)/src/gallium/state_trackers/dri/libdridrm.a \
$(TOP)/src/gallium/winsys/drm/nouveau/drm/libnouveaudrm.a \
$(TOP)/src/gallium/drivers/nv04/libnv04.a \
$(TOP)/src/gallium/drivers/nv10/libnv10.a \
$(TOP)/src/gallium/drivers/nv20/libnv20.a \
$(TOP)/src/gallium/drivers/nv30/libnv30.a \
$(TOP)/src/gallium/drivers/nv40/libnv40.a \
$(TOP)/src/gallium/drivers/nv50/libnv50.a \
src/gallium/winsys/drm/nouveau/drm/nouveau_drm_api.c
-18
View File
@@ -81,15 +81,6 @@ nouveau_drm_create_screen(struct drm_api *api, int fd,
return NULL;
switch (dev->chipset & 0xf0) {
case 0x00:
init = nv04_screen_create;
break;
case 0x10:
init = nv10_screen_create;
break;
case 0x20:
init = nv20_screen_create;
break;
case 0x30:
init = nv30_screen_create;
break;
@@ -160,15 +151,6 @@ nouveau_drm_create_context(struct drm_api *api, struct pipe_screen *pscreen)
int i;
switch (chipset & 0xf0) {
case 0x00:
init = nv04_create;
break;
case 0x10:
init = nv10_create;
break;
case 0x20:
init = nv20_create;
break;
case 0x30:
init = nv30_create;
break;
src/gallium/winsys/drm/nouveau/egl/Makefile
-3
View File
@@ -7,9 +7,6 @@ EGL_DRIVER_LIBS = -ldrm_nouveau
EGL_DRIVER_PIPES = \
$(TOP)/src/gallium/winsys/drm/nouveau/drm/libnouveaudrm.a \
$(TOP)/src/gallium/drivers/nv04/libnv04.a \
$(TOP)/src/gallium/drivers/nv10/libnv10.a \
$(TOP)/src/gallium/drivers/nv20/libnv20.a \
$(TOP)/src/gallium/drivers/nv30/libnv30.a \
$(TOP)/src/gallium/drivers/nv40/libnv40.a \
$(TOP)/src/gallium/drivers/nv50/libnv50.a \
src/gallium/winsys/drm/nouveau/xorg/Makefile
-3
View File
@@ -18,9 +18,6 @@ INCLUDES = \
LIBS = \
$(TOP)/src/gallium/state_trackers/xorg/libxorgtracker.a \
$(TOP)/src/gallium/winsys/drm/nouveau/drm/libnouveaudrm.a \
$(TOP)/src/gallium/drivers/nv04/libnv04.a \
$(TOP)/src/gallium/drivers/nv10/libnv10.a \
$(TOP)/src/gallium/drivers/nv20/libnv20.a \
$(TOP)/src/gallium/drivers/nv30/libnv30.a \
$(TOP)/src/gallium/drivers/nv40/libnv40.a \
$(TOP)/src/gallium/drivers/nv50/libnv50.a \
src/gallium/winsys/g3dvl/nouveau/Makefile
+1 -4
View File
@@ -20,14 +20,11 @@ LDFLAGS += -L${DRMDIR}/lib \
-L${DRIDIR}/lib \
-L${GALLIUMDIR}/winsys/drm/nouveau/common \
-L${GALLIUMDIR}/auxiliary \
-L${GALLIUMDIR}/drivers/nv04 \
-L${GALLIUMDIR}/drivers/nv10 \
-L${GALLIUMDIR}/drivers/nv20 \
-L${GALLIUMDIR}/drivers/nv30 \
-L${GALLIUMDIR}/drivers/nv40 \
-L${GALLIUMDIR}/drivers/nv50
LIBS += -lnouveaudrm -ldriclient -ldrm_nouveau -ldrm -lnv04 -lnv10 -lnv20 -lnv30 -lnv40 -lnv50 -lgallium -lm
LIBS += -lnouveaudrm -ldriclient -ldrm_nouveau -ldrm -lnv30 -lnv40 -lnv50 -lgallium -lm
#############################################