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radv: respect the render area for depth/stencil resolves

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Subpass resolves don't necessarily start from 0,0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17950>
This commit is contained in:
Samuel Pitoiset
2022-08-09 09:42:51 +02:00
committed by Marge Bot
parent aa5d4062e8
commit 5b5d5554f6
2 changed files with 32 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_meta_resolve_cs.c
+23 -8
View File
@@ -148,7 +148,15 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
output_img->data.descriptor_set = 0;
output_img->data.binding = 1;
nir_ssa_def *img_coord = get_global_ids(&b, 3);
nir_ssa_def *global_id = get_global_ids(&b, 3);
nir_ssa_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
nir_ssa_def *resolve_coord = nir_iadd(&b, nir_channels(&b, global_id, 0x3), offset);
nir_ssa_def *img_coord = nir_vec3(&b, nir_channel(&b, resolve_coord, 0),
nir_channel(&b, resolve_coord, 1),
nir_channel(&b, global_id, 2));
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
@@ -565,8 +573,9 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivi
static void
emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
struct radv_image_view *dest_iview, const VkExtent3D *resolve_extent,
VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode)
struct radv_image_view *dest_iview, const VkOffset2D *resolve_offset,
const VkExtent3D *resolve_extent, VkImageAspectFlags aspects,
VkResolveModeFlagBits resolve_mode)
{
struct radv_device *device = cmd_buffer->device;
const uint32_t samples = src_iview->image->info.samples;
@@ -642,6 +651,12 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
*pipeline);
uint32_t push_constants[2] = { resolve_offset->x, resolve_offset->y };
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
device->meta_state.resolve_compute.p_layout, VK_SHADER_STAGE_COMPUTE_BIT,
0, sizeof(push_constants), push_constants);
radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height,
resolve_extent->depth);
}
@@ -831,10 +846,10 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
VkImageAspectFlags aspects,
VkResolveModeFlagBits resolve_mode)
{
struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
uint32_t layer_count = cmd_buffer->state.framebuffer->layers;
VkRect2D resolve_area = cmd_buffer->state.render_area;
struct radv_meta_saved_state saved_state;
uint32_t layer_count = fb->layers;
if (subpass->view_mask)
layer_count = util_last_bit(subpass->view_mask);
@@ -903,9 +918,9 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
},
0, NULL);
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, &tdst_iview,
&(VkExtent3D){fb->width, fb->height, layer_count}, aspects,
resolve_mode);
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, &tdst_iview, &resolve_area.offset,
&(VkExtent3D){resolve_area.extent.width, resolve_area.extent.height, layer_count},
aspects, resolve_mode);
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
src/amd/vulkan/radv_meta_resolve_fs.c
+9 -8
View File
@@ -697,8 +697,9 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivi
static void
emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
struct radv_image_view *dst_iview, const VkExtent2D *resolve_extent,
VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode)
struct radv_image_view *dst_iview, const VkOffset2D *resolve_offset,
const VkExtent2D *resolve_extent, VkImageAspectFlags aspects,
VkResolveModeFlagBits resolve_mode)
{
struct radv_device *device = cmd_buffer->device;
const uint32_t samples = src_iview->image->info.samples;
@@ -767,8 +768,8 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
*pipeline);
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
&(VkViewport){.x = 0,
.y = 0,
&(VkViewport){.x = resolve_offset->x,
.y = resolve_offset->y,
.width = resolve_extent->width,
.height = resolve_extent->height,
.minDepth = 0.0f,
@@ -776,7 +777,7 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
&(VkRect2D){
.offset = (VkOffset2D){0, 0},
.offset = *resolve_offset,
.extent = *resolve_extent,
});
@@ -943,8 +944,8 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
VkImageAspectFlags aspects,
VkResolveModeFlagBits resolve_mode)
{
struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
VkRect2D resolve_area = cmd_buffer->state.render_area;
struct radv_meta_saved_state saved_state;
struct radv_subpass_barrier barrier;
@@ -1000,8 +1001,8 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
},
0, NULL);
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
&(VkExtent2D){fb->width, fb->height}, aspects, resolve_mode);
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview, &resolve_area.offset,
&resolve_area.extent, aspects, resolve_mode);
radv_cmd_buffer_restore_subpass(cmd_buffer, subpass);