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radv: add tess ctrl stage barrier workaround for SI.

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This just ports the workaround from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2017-03-30 08:13:48 +01:00
parent 3a633cc2cb
commit 5b40eab00a
1 changed files with 10 additions and 2 deletions
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src/amd/common/ac_nir_to_llvm.c
+10 -2
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@@ -2917,9 +2917,17 @@ static void emit_waitcnt(struct nir_to_llvm_context *ctx,
static void emit_barrier(struct nir_to_llvm_context *ctx)
{
// TODO tess
/* SI only (thanks to a hw bug workaround):
* The real barrier instruction isn’t needed, because an entire patch
* always fits into a single wave.
*/
if (ctx->options->chip_class == SI &&
ctx->stage == MESA_SHADER_TESS_CTRL) {
emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
return;
}
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
ctx->voidt, NULL, 0, 0);
ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
}
static void emit_discard_if(struct nir_to_llvm_context *ctx,