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r600c: properly align mipmaps to group size

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fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=31400
This commit is contained in:
Alex Deucher
2010-11-08 11:56:41 -05:00
parent 136ff67ce8
commit 5b15b5f4a8
2 changed files with 7 additions and 4 deletions
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src/mesa/drivers/dri/radeon/radeon_common_context.c
+3 -3
View File
@@ -251,9 +251,9 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
radeon->texture_rect_row_align = 512;
radeon->texture_compressed_row_align = 512;
} else {
radeon->texture_row_align = 256;
radeon->texture_rect_row_align = 256;
radeon->texture_compressed_row_align = 256;
radeon->texture_row_align = radeon->radeonScreen->group_bytes;
radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
}
} else if (IS_R200_CLASS(radeon->radeonScreen) ||
IS_R100_CLASS(radeon->radeonScreen)) {
src/mesa/drivers/dri/radeon/radeon_screen.c
+4 -1
View File
@@ -1138,6 +1138,8 @@ radeonCreateScreen( __DRIscreen *sPriv )
else
screen->chip_flags |= RADEON_CLASS_R600;
/* set group bytes for r6xx+ */
screen->group_bytes = 256;
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
@@ -1382,7 +1384,8 @@ radeonCreateScreen2(__DRIscreen *sPriv)
else
screen->chip_flags |= RADEON_CLASS_R600;
/* r6xx+ tiling */
/* r6xx+ tiling, default to 256 group bytes */
screen->group_bytes = 256;
if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)