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tgsi: rename fields of tgsi_full_dst_register to reduce verbosity

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DstRegister -> Register
DstRegisterInd -> Indirect
This commit is contained in:
Keith Whitwell
2009-11-24 15:08:55 +00:00
parent fe2b31e4a8
commit 5b0824dfe5
31 changed files with 283 additions and 283 deletions
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src/gallium/auxiliary/draw/draw_pipe_aaline.c
+12 -12
View File
@@ -265,8 +265,8 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = aactx->texTemp;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = aactx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.Instruction.Texture = TRUE;
newInst.Texture.Texture = TGSI_TEXTURE_2D;
@@ -281,9 +281,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MOV;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Instruction.NumSrcRegs = 1;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
@@ -293,9 +293,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
@@ -318,10 +318,10 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT &&
dst->DstRegister.Index == aactx->colorOutput) {
dst->DstRegister.File = TGSI_FILE_TEMPORARY;
dst->DstRegister.Index = aactx->colorTemp;
if (dst->Register.File == TGSI_FILE_OUTPUT &&
dst->Register.Index == aactx->colorOutput) {
dst->Register.File = TGSI_FILE_TEMPORARY;
dst->Register.Index = aactx->colorTemp;
}
}
src/gallium/auxiliary/draw/draw_pipe_aapoint.c
+43 -43
View File
@@ -234,9 +234,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_XY;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XY;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.Src[0].SrcRegister.Index = texInput;
@@ -248,9 +248,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_ADD;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -265,9 +265,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RSQ;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 1;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -277,9 +277,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RCP;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 1;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -290,9 +290,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SGT;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -323,9 +323,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SUB;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.Src[0].SrcRegister.Index = texInput;
@@ -339,9 +339,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RCP;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
newInst.Instruction.NumSrcRegs = 1;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -352,9 +352,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SUB;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.Src[0].SrcRegister.Index = texInput;
@@ -368,9 +368,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -384,9 +384,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SLE;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -405,9 +405,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_CMP;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = tmp0;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = tmp0;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 3;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = tmp0;
@@ -439,9 +439,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MOV;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Instruction.NumSrcRegs = 1;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
@@ -451,9 +451,9 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Dst[0].Register.File = TGSI_FILE_OUTPUT;
newInst.Dst[0].Register.Index = aactx->colorOutput;
newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
@@ -469,10 +469,10 @@ aa_transform_inst(struct tgsi_transform_context *ctx,
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT &&
dst->DstRegister.Index == aactx->colorOutput) {
dst->DstRegister.File = TGSI_FILE_TEMPORARY;
dst->DstRegister.Index = aactx->colorTemp;
if (dst->Register.File == TGSI_FILE_OUTPUT &&
dst->Register.Index == aactx->colorOutput) {
dst->Register.File = TGSI_FILE_TEMPORARY;
dst->Register.Index = aactx->colorTemp;
}
}
}
src/gallium/auxiliary/draw/draw_pipe_pstipple.c
+4 -4
View File
@@ -280,8 +280,8 @@ pstip_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = pctx->texTemp;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = pctx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
newInst.Src[0].SrcRegister.Index = wincoordInput;
@@ -293,8 +293,8 @@ pstip_transform_inst(struct tgsi_transform_context *ctx,
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
newInst.Instruction.NumDstRegs = 1;
newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].DstRegister.Index = pctx->texTemp;
newInst.Dst[0].Register.File = TGSI_FILE_TEMPORARY;
newInst.Dst[0].Register.Index = pctx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.Instruction.Texture = TRUE;
newInst.Texture.Texture = TGSI_TEXTURE_2D;
src/gallium/auxiliary/draw/draw_vs_aos.c
+25 -25
View File
@@ -361,8 +361,8 @@ static struct x86_reg aos_get_shader_reg_ptr( struct aos_compilation *cp,
static struct x86_reg get_dst_ptr( struct aos_compilation *cp,
const struct tgsi_full_dst_register *dst )
{
unsigned file = dst->DstRegister.File;
unsigned idx = dst->DstRegister.Index;
unsigned file = dst->Register.File;
unsigned idx = dst->Register.Index;
unsigned i;
@@ -669,15 +669,15 @@ static void store_dest( struct aos_compilation *cp,
{
struct x86_reg dst;
switch (reg->DstRegister.WriteMask) {
switch (reg->Register.WriteMask) {
case 0:
return;
case TGSI_WRITEMASK_XYZW:
aos_adopt_xmm_reg(cp,
get_xmm_writable(cp, result),
reg->DstRegister.File,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.Index,
TRUE);
return;
default:
@@ -685,10 +685,10 @@ static void store_dest( struct aos_compilation *cp,
}
dst = aos_get_shader_reg_xmm(cp,
reg->DstRegister.File,
reg->DstRegister.Index);
reg->Register.File,
reg->Register.Index);
switch (reg->DstRegister.WriteMask) {
switch (reg->Register.WriteMask) {
case TGSI_WRITEMASK_X:
sse_movss(cp->func, dst, get_xmm(cp, result));
break;
@@ -710,14 +710,14 @@ static void store_dest( struct aos_compilation *cp,
break;
default:
mask_write(cp, dst, result, reg->DstRegister.WriteMask);
mask_write(cp, dst, result, reg->Register.WriteMask);
break;
}
aos_adopt_xmm_reg(cp,
dst,
reg->DstRegister.File,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.Index,
TRUE);
}
@@ -737,7 +737,7 @@ static void store_scalar_dest( struct aos_compilation *cp,
const struct tgsi_full_dst_register *reg,
struct x86_reg result )
{
unsigned writemask = reg->DstRegister.WriteMask;
unsigned writemask = reg->Register.WriteMask;
struct x86_reg dst;
if (writemask != TGSI_WRITEMASK_X &&
@@ -754,12 +754,12 @@ static void store_scalar_dest( struct aos_compilation *cp,
result = get_xmm(cp, result);
dst = aos_get_shader_reg_xmm(cp,
reg->DstRegister.File,
reg->DstRegister.Index);
reg->Register.File,
reg->Register.Index);
switch (reg->DstRegister.WriteMask) {
switch (reg->Register.WriteMask) {
case TGSI_WRITEMASK_X:
sse_movss(cp->func, dst, result);
break;
@@ -782,8 +782,8 @@ static void store_scalar_dest( struct aos_compilation *cp,
aos_adopt_xmm_reg(cp,
dst,
reg->DstRegister.File,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.Index,
TRUE);
}
@@ -819,7 +819,7 @@ static void x87_fstp_dest4( struct aos_compilation *cp,
const struct tgsi_full_dst_register *dst )
{
struct x86_reg ptr = get_dst_ptr(cp, dst);
unsigned writemask = dst->DstRegister.WriteMask;
unsigned writemask = dst->Register.WriteMask;
x87_fst_or_nop(cp->func, writemask, 0, ptr);
x87_fst_or_nop(cp->func, writemask, 1, ptr);
@@ -1100,7 +1100,7 @@ static boolean emit_EX2( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_FLR( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
unsigned writemask = op->Dst[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
int i;
set_fpu_round_neg_inf( cp );
@@ -1127,7 +1127,7 @@ static boolean emit_FLR( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_RND( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
unsigned writemask = op->Dst[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
int i;
set_fpu_round_nearest( cp );
@@ -1156,7 +1156,7 @@ static boolean emit_FRC( struct aos_compilation *cp, const struct tgsi_full_inst
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
struct x86_reg st0 = x86_make_reg(file_x87, 0);
struct x86_reg st1 = x86_make_reg(file_x87, 1);
unsigned writemask = op->Dst[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
int i;
set_fpu_round_neg_inf( cp );
@@ -1190,7 +1190,7 @@ static boolean emit_FRC( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg ecx = x86_make_reg( file_REG32, reg_CX );
unsigned writemask = op->Dst[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
unsigned lit_count = cp->lit_count++;
struct x86_reg result, arg0;
unsigned i;
@@ -1270,7 +1270,7 @@ static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_inst
static boolean emit_inline_LIT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
unsigned writemask = op->Dst[0].DstRegister.WriteMask;
unsigned writemask = op->Dst[0].Register.WriteMask;
if (writemask & TGSI_WRITEMASK_YZ) {
struct x86_reg st1 = x86_make_reg(file_x87, 1);
@@ -1897,10 +1897,10 @@ static void find_last_write_outputs( struct aos_compilation *cp )
continue;
for (i = 0; i < TGSI_FULL_MAX_DST_REGISTERS; i++) {
if (parse.FullToken.FullInstruction.Dst[i].DstRegister.File ==
if (parse.FullToken.FullInstruction.Dst[i].Register.File ==
TGSI_FILE_OUTPUT)
{
unsigned idx = parse.FullToken.FullInstruction.Dst[i].DstRegister.Index;
unsigned idx = parse.FullToken.FullInstruction.Dst[i].Register.Index;
cp->output_last_write[idx] = this_instruction;
}
}
src/gallium/auxiliary/gallivm/tgsitollvm.cpp
+8 -8
View File
@@ -658,12 +658,12 @@ translate_instruction(llvm::Module *module,
for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
storage->setOutputElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
} else if (dst->DstRegister.File == TGSI_FILE_TEMPORARY) {
storage->setTempElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
} else if (dst->DstRegister.File == TGSI_FILE_ADDRESS) {
storage->setAddrElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
if (dst->Register.File == TGSI_FILE_OUTPUT) {
storage->setOutputElement(dst->Register.Index, out, dst->Register.WriteMask);
} else if (dst->Register.File == TGSI_FILE_TEMPORARY) {
storage->setTempElement(dst->Register.Index, out, dst->Register.WriteMask);
} else if (dst->Register.File == TGSI_FILE_ADDRESS) {
storage->setAddrElement(dst->Register.Index, out, dst->Register.WriteMask);
} else {
fprintf(stderr, "ERROR: unsupported LLVM destination!");
assert(!"wrong destination");
@@ -994,8 +994,8 @@ translate_instructionir(llvm::Module *module,
/* store results */
for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
struct tgsi_full_dst_register *dst = &inst->Dst[i];
storage->store((enum tgsi_file_type)dst->DstRegister.File,
dst->DstRegister.Index, out, dst->DstRegister.WriteMask,
storage->store((enum tgsi_file_type)dst->Register.File,
dst->Register.Index, out, dst->Register.WriteMask,
instr->getIRBuilder() );
}
}
src/gallium/auxiliary/tgsi/tgsi_build.c
+17 -17
View File
@@ -580,15 +580,15 @@ tgsi_build_full_instruction(
size++;
*dst_register = tgsi_build_dst_register(
reg->DstRegister.File,
reg->DstRegister.WriteMask,
reg->DstRegister.Indirect,
reg->DstRegister.Index,
reg->Register.File,
reg->Register.WriteMask,
reg->Register.Indirect,
reg->Register.Index,
instruction,
header );
prev_token = (struct tgsi_token *) dst_register;
if( reg->DstRegister.Indirect ) {
if( reg->Register.Indirect ) {
struct tgsi_src_register *ind;
if( maxsize <= size )
@@ -597,16 +597,16 @@ tgsi_build_full_instruction(
size++;
*ind = tgsi_build_src_register(
reg->DstRegisterInd.File,
reg->DstRegisterInd.SwizzleX,
reg->DstRegisterInd.SwizzleY,
reg->DstRegisterInd.SwizzleZ,
reg->DstRegisterInd.SwizzleW,
reg->DstRegisterInd.Negate,
reg->DstRegisterInd.Absolute,
reg->DstRegisterInd.Indirect,
reg->DstRegisterInd.Dimension,
reg->DstRegisterInd.Index,
reg->Indirect.File,
reg->Indirect.SwizzleX,
reg->Indirect.SwizzleY,
reg->Indirect.SwizzleZ,
reg->Indirect.SwizzleW,
reg->Indirect.Negate,
reg->Indirect.Absolute,
reg->Indirect.Indirect,
reg->Indirect.Dimension,
reg->Indirect.Index,
instruction,
header );
}
@@ -980,8 +980,8 @@ tgsi_default_full_dst_register( void )
{
struct tgsi_full_dst_register full_dst_register;
full_dst_register.DstRegister = tgsi_default_dst_register();
full_dst_register.DstRegisterInd = tgsi_default_src_register();
full_dst_register.Register = tgsi_default_dst_register();
full_dst_register.Indirect = tgsi_default_src_register();
return full_dst_register;
}
src/gallium/auxiliary/tgsi/tgsi_dump.c
+10 -10
View File
@@ -358,23 +358,23 @@ iter_instruction(
CHR( ',' );
CHR( ' ' );
if (dst->DstRegister.Indirect) {
if (dst->Register.Indirect) {
_dump_register_ind(
ctx,
dst->DstRegister.File,
dst->DstRegister.Index,
dst->DstRegisterInd.File,
dst->DstRegisterInd.Index,
dst->DstRegisterInd.SwizzleX );
dst->Register.File,
dst->Register.Index,
dst->Indirect.File,
dst->Indirect.Index,
dst->Indirect.SwizzleX );
}
else {
_dump_register(
ctx,
dst->DstRegister.File,
dst->DstRegister.Index,
dst->DstRegister.Index );
dst->Register.File,
dst->Register.Index,
dst->Register.Index );
}
_dump_writemask( ctx, dst->DstRegister.WriteMask );
_dump_writemask( ctx, dst->Register.WriteMask );
first_reg = FALSE;
}
src/gallium/auxiliary/tgsi/tgsi_dump_c.c
+19 -19
View File
@@ -339,48 +339,48 @@ dump_instruction_verbose(
EOL();
TXT( "\nFile : " );
ENM( dst->DstRegister.File, TGSI_FILES );
if( deflt || fd->DstRegister.WriteMask != dst->DstRegister.WriteMask ) {
ENM( dst->Register.File, TGSI_FILES );
if( deflt || fd->Register.WriteMask != dst->Register.WriteMask ) {
TXT( "\nWriteMask: " );
ENM( dst->DstRegister.WriteMask, TGSI_WRITEMASKS );
ENM( dst->Register.WriteMask, TGSI_WRITEMASKS );
}
if( ignored ) {
if( deflt || fd->DstRegister.Indirect != dst->DstRegister.Indirect ) {
if( deflt || fd->Register.Indirect != dst->Register.Indirect ) {
TXT( "\nIndirect : " );
UID( dst->DstRegister.Indirect );
UID( dst->Register.Indirect );
}
if( deflt || fd->DstRegister.Dimension != dst->DstRegister.Dimension ) {
if( deflt || fd->Register.Dimension != dst->Register.Dimension ) {
TXT( "\nDimension: " );
UID( dst->DstRegister.Dimension );
UID( dst->Register.Dimension );
}
}
if( deflt || fd->DstRegister.Index != dst->DstRegister.Index ) {
if( deflt || fd->Register.Index != dst->Register.Index ) {
TXT( "\nIndex : " );
SID( dst->DstRegister.Index );
SID( dst->Register.Index );
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( dst->DstRegister.Padding );
if( deflt || fd->DstRegister.Extended != dst->DstRegister.Extended ) {
UIX( dst->Register.Padding );
if( deflt || fd->Register.Extended != dst->Register.Extended ) {
TXT( "\nExtended : " );
UID( dst->DstRegister.Extended );
UID( dst->Register.Extended );
}
}
if( deflt || tgsi_compare_dst_register_ext_modulate( dst->DstRegisterExtModulate, fd->DstRegisterExtModulate ) ) {
if( deflt || tgsi_compare_dst_register_ext_modulate( dst->RegisterExtModulate, fd->RegisterExtModulate ) ) {
EOL();
TXT( "\nType : " );
ENM( dst->DstRegisterExtModulate.Type, TGSI_DST_REGISTER_EXTS );
if( deflt || fd->DstRegisterExtModulate.Modulate != dst->DstRegisterExtModulate.Modulate ) {
ENM( dst->RegisterExtModulate.Type, TGSI_DST_REGISTER_EXTS );
if( deflt || fd->RegisterExtModulate.Modulate != dst->RegisterExtModulate.Modulate ) {
TXT( "\nModulate: " );
ENM( dst->DstRegisterExtModulate.Modulate, TGSI_MODULATES );
ENM( dst->RegisterExtModulate.Modulate, TGSI_MODULATES );
}
if( ignored ) {
TXT( "\nPadding : " );
UIX( dst->DstRegisterExtModulate.Padding );
if( deflt || fd->DstRegisterExtModulate.Extended != dst->DstRegisterExtModulate.Extended ) {
UIX( dst->RegisterExtModulate.Padding );
if( deflt || fd->RegisterExtModulate.Extended != dst->RegisterExtModulate.Extended ) {
TXT( "\nExtended: " );
UID( dst->DstRegisterExtModulate.Extended );
UID( dst->RegisterExtModulate.Extended );
}
}
}
src/gallium/auxiliary/tgsi/tgsi_exec.c
+18 -18
View File
@@ -107,10 +107,10 @@
#define TEMP_P0 TGSI_EXEC_TEMP_P0
#define IS_CHANNEL_ENABLED(INST, CHAN)\
((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
((INST).Dst[1].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
@@ -188,7 +188,7 @@ tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
{
uint i, chan;
uint writemask = inst->Dst[0].DstRegister.WriteMask;
uint writemask = inst->Dst[0].Register.WriteMask;
if (writemask == TGSI_WRITEMASK_X ||
writemask == TGSI_WRITEMASK_Y ||
writemask == TGSI_WRITEMASK_Z ||
@@ -201,9 +201,9 @@ tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
/* loop over src regs */
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
if ((inst->Src[i].SrcRegister.File ==
inst->Dst[0].DstRegister.File) &&
inst->Dst[0].Register.File) &&
(inst->Src[i].SrcRegister.Index ==
inst->Dst[0].DstRegister.Index)) {
inst->Dst[0].Register.Index)) {
/* loop over dest channels */
uint channelsWritten = 0x0;
FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
@@ -1424,11 +1424,11 @@ store_dest(
*
* file[ind[2].x+1],
* where:
* ind = DstRegisterInd.File
* [2] = DstRegisterInd.Index
* .x = DstRegisterInd.SwizzleX
* ind = Indirect.File
* [2] = Indirect.Index
* .x = Indirect.SwizzleX
*/
if (reg->DstRegister.Indirect) {
if (reg->Register.Indirect) {
union tgsi_exec_channel index;
union tgsi_exec_channel indir_index;
uint swizzle;
@@ -1437,15 +1437,15 @@ store_dest(
index.i[0] =
index.i[1] =
index.i[2] =
index.i[3] = reg->DstRegisterInd.Index;
index.i[3] = reg->Indirect.Index;
/* get current value of address register[swizzle] */
swizzle = tgsi_util_get_src_register_swizzle( &reg->DstRegisterInd, CHAN_X );
swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
/* fetch values from the address/indirection register */
fetch_src_file_channel(
mach,
reg->DstRegisterInd.File,
reg->Indirect.File,
swizzle,
&index,
&indir_index );
@@ -1454,37 +1454,37 @@ store_dest(
offset = (int) indir_index.f[0];
}
switch (reg->DstRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_NULL:
dst = &null;
break;
case TGSI_FILE_OUTPUT:
index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
+ reg->DstRegister.Index;
+ reg->Register.Index;
dst = &mach->Outputs[offset + index].xyzw[chan_index];
break;
case TGSI_FILE_TEMPORARY:
index = reg->DstRegister.Index;
index = reg->Register.Index;
assert( index < TGSI_EXEC_NUM_TEMPS );
dst = &mach->Temps[offset + index].xyzw[chan_index];
break;
case TGSI_FILE_ADDRESS:
index = reg->DstRegister.Index;
index = reg->Register.Index;
dst = &mach->Addrs[index].xyzw[chan_index];
break;
case TGSI_FILE_LOOP:
assert(reg->DstRegister.Index == 0);
assert(reg->Register.Index == 0);
assert(mach->LoopCounterStackTop > 0);
assert(chan_index == CHAN_X);
dst = &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[chan_index];
break;
case TGSI_FILE_PREDICATE:
index = reg->DstRegister.Index;
index = reg->Register.Index;
assert(index < TGSI_EXEC_NUM_PREDS);
dst = &mach->Predicates[index].xyzw[chan_index];
break;
src/gallium/auxiliary/tgsi/tgsi_parse.c
+6 -6
View File
@@ -168,21 +168,21 @@ tgsi_parse_token(
for( i = 0; i < inst->Instruction.NumDstRegs; i++ ) {
next_token( ctx, &inst->Dst[i].DstRegister );
next_token( ctx, &inst->Dst[i].Register );
/*
* No support for indirect or multi-dimensional addressing.
*/
assert( !inst->Dst[i].DstRegister.Dimension );
assert( !inst->Dst[i].Register.Dimension );
if( inst->Dst[i].DstRegister.Indirect ) {
next_token( ctx, &inst->Dst[i].DstRegisterInd );
if( inst->Dst[i].Register.Indirect ) {
next_token( ctx, &inst->Dst[i].Indirect );
/*
* No support for indirect or multi-dimensional addressing.
*/
assert( !inst->Dst[i].DstRegisterInd.Dimension );
assert( !inst->Dst[i].DstRegisterInd.Indirect );
assert( !inst->Dst[i].Indirect.Dimension );
assert( !inst->Dst[i].Indirect.Indirect );
}
}
src/gallium/auxiliary/tgsi/tgsi_parse.h
+2 -2
View File
@@ -47,8 +47,8 @@ struct tgsi_full_header
struct tgsi_full_dst_register
{
struct tgsi_dst_register DstRegister;
struct tgsi_src_register DstRegisterInd;
struct tgsi_dst_register Register;
struct tgsi_src_register Indirect;
};
struct tgsi_full_src_register
src/gallium/auxiliary/tgsi/tgsi_ppc.c
+9 -9
View File
@@ -60,7 +60,7 @@ const float ppc_builtin_constants[] ALIGN16_ATTRIB = {
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
@@ -167,8 +167,8 @@ is_ppc_vec_temporary(const struct tgsi_full_src_register *reg)
static boolean
is_ppc_vec_temporary_dst(const struct tgsi_full_dst_register *reg)
{
return (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Index < MAX_PPC_TEMPS);
return (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Index < MAX_PPC_TEMPS);
}
@@ -485,7 +485,7 @@ get_dst_vec(struct gen_context *gen,
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
if (is_ppc_vec_temporary_dst(reg)) {
int vec = gen->temps_map[reg->DstRegister.Index][chan_index];
int vec = gen->temps_map[reg->Register.Index][chan_index];
return vec;
}
else {
@@ -507,10 +507,10 @@ emit_store(struct gen_context *gen,
{
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
switch (reg->DstRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_OUTPUT:
{
int offset = (reg->DstRegister.Index * 4 + chan_index) * 16;
int offset = (reg->Register.Index * 4 + chan_index) * 16;
int offset_reg = emit_li_offset(gen, offset);
ppc_stvx(gen->f, src_vec, gen->outputs_reg, offset_reg);
}
@@ -518,14 +518,14 @@ emit_store(struct gen_context *gen,
case TGSI_FILE_TEMPORARY:
if (is_ppc_vec_temporary_dst(reg)) {
if (!free_vec) {
int dst_vec = gen->temps_map[reg->DstRegister.Index][chan_index];
int dst_vec = gen->temps_map[reg->Register.Index][chan_index];
if (dst_vec != src_vec)
ppc_vmove(gen->f, dst_vec, src_vec);
}
free_vec = FALSE;
}
else {
int offset = (reg->DstRegister.Index * 4 + chan_index) * 16;
int offset = (reg->Register.Index * 4 + chan_index) * 16;
int offset_reg = emit_li_offset(gen, offset);
ppc_stvx(gen->f, src_vec, gen->temps_reg, offset_reg);
}
@@ -535,7 +535,7 @@ emit_store(struct gen_context *gen,
emit_addrs(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
#endif
src/gallium/auxiliary/tgsi/tgsi_sanity.c
+4 -4
View File
@@ -212,8 +212,8 @@ iter_instruction(
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
check_register_usage(
ctx,
inst->Dst[i].DstRegister.File,
inst->Dst[i].DstRegister.Index,
inst->Dst[i].Register.File,
inst->Dst[i].Register.Index,
"destination",
FALSE );
}
@@ -245,8 +245,8 @@ iter_instruction(
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_BGNFOR:
case TGSI_OPCODE_ENDFOR:
if (inst->Dst[0].DstRegister.File != TGSI_FILE_LOOP ||
inst->Dst[0].DstRegister.Index != 0) {
if (inst->Dst[0].Register.File != TGSI_FILE_LOOP ||
inst->Dst[0].Register.Index != 0) {
report_error(ctx, "Destination register must be LOOP[0]");
}
break;
src/gallium/auxiliary/tgsi/tgsi_scan.c
+3 -3
View File
@@ -212,8 +212,8 @@ tgsi_is_passthrough_shader(const struct tgsi_token *tokens)
/* Do a whole bunch of checks for a simple move */
if (fullinst->Instruction.Opcode != TGSI_OPCODE_MOV ||
src->SrcRegister.File != TGSI_FILE_INPUT ||
dst->DstRegister.File != TGSI_FILE_OUTPUT ||
src->SrcRegister.Index != dst->DstRegister.Index ||
dst->Register.File != TGSI_FILE_OUTPUT ||
src->SrcRegister.Index != dst->Register.Index ||
src->SrcRegister.Negate ||
src->SrcRegister.Absolute ||
@@ -223,7 +223,7 @@ tgsi_is_passthrough_shader(const struct tgsi_token *tokens)
src->SrcRegister.SwizzleZ != TGSI_SWIZZLE_Z ||
src->SrcRegister.SwizzleW != TGSI_SWIZZLE_W ||
dst->DstRegister.WriteMask != TGSI_WRITEMASK_XYZW)
dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
{
tgsi_parse_free(&parse);
return FALSE;
src/gallium/auxiliary/tgsi/tgsi_sse2.c
+7 -7
View File
@@ -58,7 +58,7 @@
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
@@ -1371,12 +1371,12 @@ emit_store(
}
switch( reg->DstRegister.File ) {
switch( reg->Register.File ) {
case TGSI_FILE_OUTPUT:
emit_output(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
@@ -1384,7 +1384,7 @@ emit_store(
emit_temps(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
@@ -1392,7 +1392,7 @@ emit_store(
emit_addrs(
func,
xmm,
reg->DstRegister.Index,
reg->Register.Index,
chan_index );
break;
@@ -1727,8 +1727,8 @@ indirect_temp_reference(const struct tgsi_full_instruction *inst)
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *reg = &inst->Dst[i];
if (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Indirect)
if (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Indirect)
return TRUE;
}
return FALSE;
src/gallium/auxiliary/tgsi/tgsi_text.c
+3 -3
View File
@@ -506,9 +506,9 @@ parse_dst_operand(
if (!parse_opt_writemask( ctx, &writemask ))
return FALSE;
dst->DstRegister.File = file;
dst->DstRegister.Index = index;
dst->DstRegister.WriteMask = writemask;
dst->Register.File = file;
dst->Register.Index = index;
dst->Register.WriteMask = writemask;
return TRUE;
}
src/gallium/auxiliary/vl/vl_compositor.c
+1 -1
View File
@@ -213,7 +213,7 @@ create_frag_shader(struct vl_compositor *c)
*/
for (i = 0; i < 4; ++i) {
inst = vl_inst3(TGSI_OPCODE_DP4, TGSI_FILE_OUTPUT, 0, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_CONSTANT, i);
inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
src/gallium/auxiliary/vl/vl_mpeg12_mc_renderer.c
+3 -3
View File
@@ -240,7 +240,7 @@ create_intra_frag_shader(struct vl_mpeg12_mc_renderer *r)
inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
@@ -418,7 +418,7 @@ create_frame_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
@@ -623,7 +623,7 @@ create_frame_bi_pred_frag_shader(struct vl_mpeg12_mc_renderer *r)
inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
src/gallium/auxiliary/vl/vl_shader_build.c
+8 -8
View File
@@ -138,8 +138,8 @@ struct tgsi_full_instruction vl_inst2
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
inst.Dst[0].DstRegister.File = dst_file;
inst.Dst[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 1;
inst.Src[0].SrcRegister.File = src_file;
inst.Src[0].SrcRegister.Index = src_index;
@@ -162,8 +162,8 @@ struct tgsi_full_instruction vl_inst3
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
inst.Dst[0].DstRegister.File = dst_file;
inst.Dst[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 2;
inst.Src[0].SrcRegister.File = src1_file;
inst.Src[0].SrcRegister.Index = src1_index;
@@ -188,8 +188,8 @@ struct tgsi_full_instruction vl_tex
inst.Instruction.Opcode = TGSI_OPCODE_TEX;
inst.Instruction.NumDstRegs = 1;
inst.Dst[0].DstRegister.File = dst_file;
inst.Dst[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 2;
inst.Instruction.Texture = 1;
inst.Texture.Texture = tex;
@@ -218,8 +218,8 @@ struct tgsi_full_instruction vl_inst4
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
inst.Dst[0].DstRegister.File = dst_file;
inst.Dst[0].DstRegister.Index = dst_index;
inst.Dst[0].Register.File = dst_file;
inst.Dst[0].Register.Index = dst_index;
inst.Instruction.NumSrcRegs = 3;
inst.Src[0].SrcRegister.File = src1_file;
inst.Src[0].SrcRegister.Index = src1_index;
src/gallium/drivers/cell/ppu/cell_gen_fp.c
+10 -10
View File
@@ -249,7 +249,7 @@ static boolean
is_memory_dst(struct codegen *gen, int channel,
const struct tgsi_full_dst_register *dst)
{
if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
if (dst->Register.File == TGSI_FILE_OUTPUT) {
return TRUE;
}
else {
@@ -374,12 +374,12 @@ get_dst_reg(struct codegen *gen,
{
int reg = -1;
switch (dest->DstRegister.File) {
switch (dest->Register.File) {
case TGSI_FILE_TEMPORARY:
if (gen->if_nesting > 0 || gen->loop_nesting > 0)
reg = get_itemp(gen);
else
reg = gen->temp_regs[dest->DstRegister.Index][channel];
reg = gen->temp_regs[dest->Register.Index][channel];
break;
case TGSI_FILE_OUTPUT:
reg = get_itemp(gen);
@@ -419,10 +419,10 @@ store_dest_reg(struct codegen *gen,
}
#endif
switch (dest->DstRegister.File) {
switch (dest->Register.File) {
case TGSI_FILE_TEMPORARY:
if (gen->if_nesting > 0 || gen->loop_nesting > 0) {
int d_reg = gen->temp_regs[dest->DstRegister.Index][channel];
int d_reg = gen->temp_regs[dest->Register.Index][channel];
int exec_reg = get_exec_mask_reg(gen);
/* Mix d with new value according to exec mask:
* d[i] = mask_reg[i] ? value_reg : d_reg
@@ -437,7 +437,7 @@ store_dest_reg(struct codegen *gen,
case TGSI_FILE_OUTPUT:
{
/* offset is measured in quadwords, not bytes */
int offset = dest->DstRegister.Index * 4 + channel;
int offset = dest->Register.Index * 4 + channel;
if (gen->if_nesting > 0 || gen->loop_nesting > 0) {
int exec_reg = get_exec_mask_reg(gen);
int curval_reg = get_itemp(gen);
@@ -544,7 +544,7 @@ emit_epilogue(struct codegen *gen)
#define FOR_EACH_ENABLED_CHANNEL(inst, ch) \
for (ch = 0; ch < 4; ch++) \
if (inst->Dst[0].DstRegister.WriteMask & (1 << ch))
if (inst->Dst[0].Register.WriteMask & (1 << ch))
static boolean
@@ -948,7 +948,7 @@ emit_XPD(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* t = y0 * z1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
if (inst->Dst[0].DstRegister.WriteMask & (1 << CHAN_X)) {
if (inst->Dst[0].Register.WriteMask & (1 << CHAN_X)) {
store_dest_reg(gen, tmp_reg, CHAN_X, &inst->Dst[0]);
}
@@ -962,7 +962,7 @@ emit_XPD(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* t = z0 * x1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
if (inst->Dst[0].DstRegister.WriteMask & (1 << CHAN_Y)) {
if (inst->Dst[0].Register.WriteMask & (1 << CHAN_Y)) {
store_dest_reg(gen, tmp_reg, CHAN_Y, &inst->Dst[0]);
}
@@ -976,7 +976,7 @@ emit_XPD(struct codegen *gen, const struct tgsi_full_instruction *inst)
/* t = x0 * y1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
if (inst->Dst[0].DstRegister.WriteMask & (1 << CHAN_Z)) {
if (inst->Dst[0].Register.WriteMask & (1 << CHAN_Z)) {
store_dest_reg(gen, tmp_reg, CHAN_Z, &inst->Dst[0]);
}
src/gallium/drivers/cell/spu/spu_exec.c
+6 -6
View File
@@ -108,10 +108,10 @@
for (CHAN = 0; CHAN < 4; CHAN++)
#define IS_CHANNEL_ENABLED(INST, CHAN)\
((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
((INST).Dst[1].DstRegister.WriteMask & (1 << (CHAN)))
((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
FOR_EACH_CHANNEL( CHAN )\
@@ -532,21 +532,21 @@ store_dest(
{
union spu_exec_channel *dst;
switch( reg->DstRegister.File ) {
switch( reg->Register.File ) {
case TGSI_FILE_NULL:
return;
case TGSI_FILE_OUTPUT:
dst = &mach->Outputs[mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
+ reg->DstRegister.Index].xyzw[chan_index];
+ reg->Register.Index].xyzw[chan_index];
break;
case TGSI_FILE_TEMPORARY:
dst = &mach->Temps[reg->DstRegister.Index].xyzw[chan_index];
dst = &mach->Temps[reg->Register.Index].xyzw[chan_index];
break;
case TGSI_FILE_ADDRESS:
dst = &mach->Addrs[reg->DstRegister.Index].xyzw[chan_index];
dst = &mach->Addrs[reg->Register.Index].xyzw[chan_index];
break;
default:
src/gallium/drivers/i915/i915_fpc_translate.c
+5 -5
View File
@@ -246,10 +246,10 @@ static uint
get_result_vector(struct i915_fp_compile *p,
const struct tgsi_full_dst_register *dest)
{
switch (dest->DstRegister.File) {
switch (dest->Register.File) {
case TGSI_FILE_OUTPUT:
{
uint sem_name = p->shader->info.output_semantic_name[dest->DstRegister.Index];
uint sem_name = p->shader->info.output_semantic_name[dest->Register.Index];
switch (sem_name) {
case TGSI_SEMANTIC_POSITION:
return UREG(REG_TYPE_OD, 0);
@@ -261,7 +261,7 @@ get_result_vector(struct i915_fp_compile *p,
}
}
case TGSI_FILE_TEMPORARY:
return UREG(REG_TYPE_R, dest->DstRegister.Index);
return UREG(REG_TYPE_R, dest->Register.Index);
default:
i915_program_error(p, "Bad inst->DstReg.File");
return 0;
@@ -276,7 +276,7 @@ static uint
get_result_flags(const struct tgsi_full_instruction *inst)
{
const uint writeMask
= inst->Dst[0].DstRegister.WriteMask;
= inst->Dst[0].Register.WriteMask;
uint flags = 0x0;
if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
@@ -738,7 +738,7 @@ i915_translate_instruction(struct i915_fp_compile *p,
swizzle(tmp, X, Y, X, Y),
swizzle(tmp, X, X, ONE, ONE), 0);
writemask = inst->Dst[0].DstRegister.WriteMask;
writemask = inst->Dst[0].Register.WriteMask;
if (writemask & TGSI_WRITEMASK_Y) {
uint tmp1;
src/gallium/drivers/llvmpipe/lp_bld_tgsi_soa.c
+6 -6
View File
@@ -64,7 +64,7 @@
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
((INST)->Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
@@ -287,13 +287,13 @@ emit_store(
assert(0);
}
switch( reg->DstRegister.File ) {
switch( reg->Register.File ) {
case TGSI_FILE_OUTPUT:
bld->outputs[reg->DstRegister.Index][chan_index] = value;
bld->outputs[reg->Register.Index][chan_index] = value;
break;
case TGSI_FILE_TEMPORARY:
bld->temps[reg->DstRegister.Index][chan_index] = value;
bld->temps[reg->Register.Index][chan_index] = value;
break;
case TGSI_FILE_ADDRESS:
@@ -430,8 +430,8 @@ indirect_temp_reference(const struct tgsi_full_instruction *inst)
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *reg = &inst->Dst[i];
if (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Indirect)
if (reg->Register.File == TGSI_FILE_TEMPORARY &&
reg->Register.Indirect)
return TRUE;
}
return FALSE;
src/gallium/drivers/nv20/nv20_vertprog.c
+4 -4
View File
@@ -286,14 +286,14 @@ static INLINE struct nv20_sreg
tgsi_dst(struct nv20_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv20_sreg dst;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = nv20_sr(NV30SR_OUTPUT,
vpc->output_map[fdst->DstRegister.Index]);
vpc->output_map[fdst->Register.Index]);
break;
case TGSI_FILE_TEMPORARY:
dst = nv20_sr(NV30SR_TEMP, fdst->DstRegister.Index);
dst = nv20_sr(NV30SR_TEMP, fdst->Register.Index);
if (vpc->high_temp < dst.index)
vpc->high_temp = dst.index;
break;
@@ -379,7 +379,7 @@ nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
}
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
src/gallium/drivers/nv30/nv30_fragprog.c
+5 -5
View File
@@ -281,22 +281,22 @@ static INLINE struct nv30_sreg
tgsi_dst(struct nv30_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
int idx;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
if (fdst->DstRegister.Index == fpc->colour_id)
if (fdst->Register.Index == fpc->colour_id)
return nv30_sr(NV30SR_OUTPUT, 0);
else
return nv30_sr(NV30SR_OUTPUT, 1);
break;
case TGSI_FILE_TEMPORARY:
idx = fdst->DstRegister.Index + 1;
idx = fdst->Register.Index + 1;
if (fpc->high_temp < idx)
fpc->high_temp = idx;
return nv30_sr(NV30SR_TEMP, idx);
case TGSI_FILE_NULL:
return nv30_sr(NV30SR_NONE, 0);
default:
NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
return nv30_sr(NV30SR_NONE, 0);
}
}
@@ -424,7 +424,7 @@ nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
}
dst = tgsi_dst(fpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
switch (finst->Instruction.Opcode) {
src/gallium/drivers/nv30/nv30_vertprog.c
+4 -4
View File
@@ -286,14 +286,14 @@ static INLINE struct nv30_sreg
tgsi_dst(struct nv30_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv30_sreg dst;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = nv30_sr(NV30SR_OUTPUT,
vpc->output_map[fdst->DstRegister.Index]);
vpc->output_map[fdst->Register.Index]);
break;
case TGSI_FILE_TEMPORARY:
dst = nv30_sr(NV30SR_TEMP, fdst->DstRegister.Index);
dst = nv30_sr(NV30SR_TEMP, fdst->Register.Index);
if (vpc->high_temp < dst.index)
vpc->high_temp = dst.index;
break;
@@ -379,7 +379,7 @@ nv30_vertprog_parse_instruction(struct nv30_vpc *vpc,
}
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
src/gallium/drivers/nv40/nv40_fragprog.c
+5 -5
View File
@@ -290,15 +290,15 @@ tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc)
static INLINE struct nv40_sreg
tgsi_dst(struct nv40_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
return fpc->r_result[fdst->DstRegister.Index];
return fpc->r_result[fdst->Register.Index];
case TGSI_FILE_TEMPORARY:
return fpc->r_temp[fdst->DstRegister.Index];
return fpc->r_temp[fdst->Register.Index];
case TGSI_FILE_NULL:
return nv40_sr(NV40SR_NONE, 0);
default:
NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
return nv40_sr(NV40SR_NONE, 0);
}
}
@@ -434,7 +434,7 @@ nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
}
dst = tgsi_dst(fpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
switch (finst->Instruction.Opcode) {
src/gallium/drivers/nv40/nv40_vertprog.c
+8 -8
View File
@@ -326,15 +326,15 @@ static INLINE struct nv40_sreg
tgsi_dst(struct nv40_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
struct nv40_sreg dst;
switch (fdst->DstRegister.File) {
switch (fdst->Register.File) {
case TGSI_FILE_OUTPUT:
dst = vpc->r_result[fdst->DstRegister.Index];
dst = vpc->r_result[fdst->Register.Index];
break;
case TGSI_FILE_TEMPORARY:
dst = vpc->r_temp[fdst->DstRegister.Index];
dst = vpc->r_temp[fdst->Register.Index];
break;
case TGSI_FILE_ADDRESS:
dst = vpc->r_address[fdst->DstRegister.Index];
dst = vpc->r_address[fdst->Register.Index];
break;
default:
NOUVEAU_ERR("bad dst file\n");
@@ -470,7 +470,7 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
}
dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
@@ -683,9 +683,9 @@ nv40_vertprog_prepare(struct nv40_vpc *vpc)
finst = &p.FullToken.FullInstruction;
fdst = &finst->Dst[0];
if (fdst->DstRegister.File == TGSI_FILE_ADDRESS) {
if (fdst->DstRegister.Index > high_addr)
high_addr = fdst->DstRegister.Index;
if (fdst->Register.File == TGSI_FILE_ADDRESS) {
if (fdst->Register.Index > high_addr)
high_addr = fdst->Register.Index;
}
}
src/gallium/drivers/nv50/nv50_program.c
+18 -18
View File
@@ -1549,7 +1549,7 @@ negate_supported(const struct tgsi_full_instruction *insn, int i)
static unsigned
nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
{
unsigned x, mask = insn->Dst[0].DstRegister.WriteMask;
unsigned x, mask = insn->Dst[0].Register.WriteMask;
switch (insn->Instruction.Opcode) {
case TGSI_OPCODE_COS:
@@ -1612,17 +1612,17 @@ nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
static struct nv50_reg *
tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
{
switch (dst->DstRegister.File) {
switch (dst->Register.File) {
case TGSI_FILE_TEMPORARY:
return &pc->temp[dst->DstRegister.Index * 4 + c];
return &pc->temp[dst->Register.Index * 4 + c];
case TGSI_FILE_OUTPUT:
return &pc->result[dst->DstRegister.Index * 4 + c];
return &pc->result[dst->Register.Index * 4 + c];
case TGSI_FILE_ADDRESS:
{
struct nv50_reg *r = pc->addr[dst->DstRegister.Index * 4 + c];
struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
if (!r) {
r = alloc_addr(pc, NULL);
pc->addr[dst->DstRegister.Index * 4 + c] = r;
pc->addr[dst->Register.Index * 4 + c] = r;
}
assert(r);
return r;
@@ -1850,7 +1850,7 @@ nv50_program_tx_insn(struct nv50_pc *pc,
unsigned mask, sat, unit;
int i, c;
mask = inst->Dst[0].DstRegister.WriteMask;
mask = inst->Dst[0].Register.WriteMask;
sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
memset(src, 0, sizeof(src));
@@ -2264,7 +2264,7 @@ prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
const struct tgsi_dst_register *dst;
unsigned i, c, k, mask;
dst = &insn->Dst[0].DstRegister;
dst = &insn->Dst[0].Register;
mask = dst->WriteMask;
if (dst->File == TGSI_FILE_TEMPORARY)
@@ -2359,13 +2359,13 @@ static struct nv50_reg *
tgsi_broadcast_dst(struct nv50_pc *pc,
const struct tgsi_full_dst_register *fd, unsigned mask)
{
if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) {
int c = ffs(~mask & fd->DstRegister.WriteMask);
if (fd->Register.File == TGSI_FILE_TEMPORARY) {
int c = ffs(~mask & fd->Register.WriteMask);
if (c)
return tgsi_dst(pc, c - 1, fd);
} else {
int c = ffs(fd->DstRegister.WriteMask) - 1;
if ((1 << c) == fd->DstRegister.WriteMask)
int c = ffs(fd->Register.WriteMask) - 1;
if ((1 << c) == fd->Register.WriteMask)
return tgsi_dst(pc, c, fd);
}
@@ -2391,8 +2391,8 @@ nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
boolean neg_supp = negate_supported(insn, i);
fs = &insn->Src[i];
if (fs->SrcRegister.File != fd->DstRegister.File ||
fs->SrcRegister.Index != fd->DstRegister.Index)
if (fs->SrcRegister.File != fd->Register.File ||
fs->SrcRegister.Index != fd->Register.Index)
continue;
for (chn = 0; chn < 4; ++chn) {
@@ -2403,7 +2403,7 @@ nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
c = tgsi_util_get_full_src_register_swizzle(fs, chn);
s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
if (!(fd->DstRegister.WriteMask & (1 << c)))
if (!(fd->Register.WriteMask & (1 << c)))
continue;
/* no danger if src is copied to TEMP first */
@@ -2446,10 +2446,10 @@ nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
for (i = 0; i < 4; ++i) {
assert(pc->r_dst[m[i]] == NULL);
insn.Dst[0].DstRegister.WriteMask =
fd->DstRegister.WriteMask & (1 << m[i]);
insn.Dst[0].Register.WriteMask =
fd->Register.WriteMask & (1 << m[i]);
if (!insn.Dst[0].DstRegister.WriteMask)
if (!insn.Dst[0].Register.WriteMask)
continue;
if (deqs & (1 << i))
src/gallium/drivers/r300/r300_tgsi_to_rc.c
+4 -4
View File
@@ -190,10 +190,10 @@ static void transform_dstreg(
struct rc_dst_register * dst,
struct tgsi_full_dst_register * src)
{
dst->File = translate_register_file(src->DstRegister.File);
dst->Index = translate_register_index(ttr, src->DstRegister.File, src->DstRegister.Index);
dst->WriteMask = src->DstRegister.WriteMask;
dst->RelAddr = src->DstRegister.Indirect;
dst->File = translate_register_file(src->Register.File);
dst->Index = translate_register_index(ttr, src->Register.File, src->Register.Index);
dst->WriteMask = src->Register.WriteMask;
dst->RelAddr = src->Register.Indirect;
}
static void transform_srcreg(
src/gallium/drivers/svga/svga_tgsi_insn.c
+6 -6
View File
@@ -99,21 +99,21 @@ translate_dst_register( struct svga_shader_emitter *emit,
const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
SVGA3dShaderDestToken dest;
switch (reg->DstRegister.File) {
switch (reg->Register.File) {
case TGSI_FILE_OUTPUT:
/* Output registers encode semantic information in their name.
* Need to lookup a table built at decl time:
*/
dest = emit->output_map[reg->DstRegister.Index];
dest = emit->output_map[reg->Register.Index];
break;
default:
dest = dst_register( translate_file( reg->DstRegister.File ),
reg->DstRegister.Index );
dest = dst_register( translate_file( reg->Register.File ),
reg->Register.Index );
break;
}
dest.mask = reg->DstRegister.WriteMask;
dest.mask = reg->Register.WriteMask;
if (insn->Instruction.Saturate)
dest.dstMod = SVGA3DDSTMOD_SATURATE;
@@ -1434,7 +1434,7 @@ static boolean emit_pow(struct svga_shader_emitter *emit,
boolean need_tmp = FALSE;
/* POW can only output to a temporary */
if (insn->Dst[0].DstRegister.File != TGSI_FILE_TEMPORARY)
if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
need_tmp = TRUE;
/* POW src1 must not be the same register as dst */