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nir: Rename nir_get_io_vertex_index_src and include per-primitive I/O.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13466>
This commit is contained in:
Timur Kristóf
2021-10-14 18:14:12 +02:00
committed by Marge Bot
parent 008f5a127c
commit 5aa39253cb
8 changed files with 15 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_nir_lower_esgs_io_to_mem.c
+1 -1
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@@ -192,7 +192,7 @@ gs_per_vertex_input_offset(nir_builder *b,
lower_esgs_io_state *st,
nir_intrinsic_instr *instr)
{
nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
nir_src *vertex_src = nir_get_io_arrayed_index_src(instr);
nir_ssa_def *vertex_offset = st->chip_class >= GFX9
? gs_per_vertex_input_vertex_offset_gfx9(b, vertex_src)
: gs_per_vertex_input_vertex_offset_gfx6(b, vertex_src);
src/amd/common/ac_nir_lower_tess_io_to_mem.c
+4 -4
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@@ -253,7 +253,7 @@ filter_load_tcs_per_vertex_input(const nir_instr *instr,
* can use temporaries, no need to use shared memory.
*/
nir_src *off_src = nir_get_io_offset_src(intrin);
nir_src *vertex_index_src = nir_get_io_vertex_index_src(intrin);
nir_src *vertex_index_src = nir_get_io_arrayed_index_src(intrin);
nir_instr *vertex_index_instr = vertex_index_src->ssa->parent_instr;
bool can_use_temps = nir_src_is_const(*off_src) &&
@@ -275,7 +275,7 @@ hs_per_vertex_input_lds_offset(nir_builder *b,
nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride);
nir_ssa_def *tcs_in_current_patch_offset = nir_imul(b, rel_patch_id, tcs_in_patch_stride);
nir_ssa_def *vertex_index = nir_get_io_vertex_index_src(instr)->ssa;
nir_ssa_def *vertex_index = nir_get_io_arrayed_index_src(instr)->ssa;
nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride);
nir_ssa_def *io_offset = nir_build_calc_io_offset(b, instr, nir_imm_int(b, 16u), 4u);
@@ -310,7 +310,7 @@ hs_output_lds_offset(nir_builder *b,
nir_ssa_def *output_patch_offset = nir_iadd_nuw(b, patch_offset, output_patch0_offset);
if (per_vertex) {
nir_ssa_def *vertex_index = nir_ssa_for_src(b, *nir_get_io_vertex_index_src(intrin), 1);
nir_ssa_def *vertex_index = nir_ssa_for_src(b, *nir_get_io_arrayed_index_src(intrin), 1);
nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size);
off = nir_iadd_nuw(b, off, vertex_index_off);
@@ -337,7 +337,7 @@ hs_per_vertex_output_vmem_offset(nir_builder *b,
nir_ssa_def *rel_patch_id = nir_build_load_tess_rel_patch_id_amd(b);
nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u));
nir_ssa_def *vertex_index = nir_ssa_for_src(b, *nir_get_io_vertex_index_src(intrin), 1);
nir_ssa_def *vertex_index = nir_ssa_for_src(b, *nir_get_io_arrayed_index_src(intrin), 1);
nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u);
return nir_iadd_nuw(b, nir_iadd_nuw(b, patch_offset, vertex_index_off), io_offset);
src/amd/compiler/aco_instruction_selection.cpp
+1 -1
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@@ -4716,7 +4716,7 @@ load_input_from_temps(isel_context* ctx, nir_intrinsic_instr* instr, Temp dst)
return false;
nir_src* off_src = nir_get_io_offset_src(instr);
nir_src* vertex_index_src = nir_get_io_vertex_index_src(instr);
nir_src* vertex_index_src = nir_get_io_arrayed_index_src(instr);
nir_instr* vertex_index_instr = vertex_index_src->ssa->parent_instr;
bool can_use_temps =
nir_src_is_const(*off_src) && vertex_index_instr->type == nir_instr_type_intrinsic &&
src/amd/llvm/ac_nir_to_llvm.c
+2 -2
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@@ -2323,7 +2323,7 @@ static void visit_store_output(struct ac_nir_context *ctx, nir_intrinsic_instr *
writemask <<= component;
if (ctx->stage == MESA_SHADER_TESS_CTRL) {
nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
nir_src *vertex_index_src = nir_get_io_arrayed_index_src(instr);
LLVMValueRef vertex_index = vertex_index_src ? get_src(ctx, *vertex_index_src) : NULL;
unsigned location = nir_intrinsic_io_semantics(instr).location;
@@ -3379,7 +3379,7 @@ static LLVMValueRef visit_load(struct ac_nir_context *ctx, nir_intrinsic_instr *
unsigned base = nir_intrinsic_base(instr);
unsigned component = nir_intrinsic_component(instr);
unsigned count = instr->dest.ssa.num_components;
nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
nir_src *vertex_index_src = nir_get_io_arrayed_index_src(instr);
LLVMValueRef vertex_index = vertex_index_src ? get_src(ctx, *vertex_index_src) : NULL;
nir_src offset = *nir_get_io_offset_src(instr);
LLVMValueRef indir_index = NULL;
src/compiler/nir/nir.h
+1 -1
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@@ -4974,7 +4974,7 @@ nir_lower_shader_calls(nir_shader *shader,
void *mem_ctx);
nir_src *nir_get_io_offset_src(nir_intrinsic_instr *instr);
nir_src *nir_get_io_vertex_index_src(nir_intrinsic_instr *instr);
nir_src *nir_get_io_arrayed_index_src(nir_intrinsic_instr *instr);
nir_src *nir_get_shader_call_payload_src(nir_intrinsic_instr *call);
bool nir_is_arrayed_io(const nir_variable *var, gl_shader_stage stage);
src/compiler/nir/nir_gather_info.c
+2 -2
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@@ -527,7 +527,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_load_per_vertex_input &&
!src_is_invocation_id(nir_get_io_vertex_index_src(instr)))
!src_is_invocation_id(nir_get_io_arrayed_index_src(instr)))
shader->info.tess.tcs_cross_invocation_inputs_read |= slot_mask;
break;
@@ -550,7 +550,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_load_per_vertex_output &&
!src_is_invocation_id(nir_get_io_vertex_index_src(instr)))
!src_is_invocation_id(nir_get_io_arrayed_index_src(instr)))
shader->info.tess.tcs_cross_invocation_outputs_read |= slot_mask;
if (shader->info.stage == MESA_SHADER_FRAGMENT &&
src/compiler/nir/nir_lower_io.c
+3 -1
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@@ -2513,13 +2513,15 @@ nir_get_io_offset_src(nir_intrinsic_instr *instr)
* Return the vertex index source for a load/store per_vertex intrinsic.
*/
nir_src *
nir_get_io_vertex_index_src(nir_intrinsic_instr *instr)
nir_get_io_arrayed_index_src(nir_intrinsic_instr *instr)
{
switch (instr->intrinsic) {
case nir_intrinsic_load_per_vertex_input:
case nir_intrinsic_load_per_vertex_output:
case nir_intrinsic_load_per_primitive_output:
return &instr->src[0];
case nir_intrinsic_store_per_vertex_output:
case nir_intrinsic_store_per_primitive_output:
return &instr->src[1];
default:
return NULL;
src/intel/compiler/brw_nir.c
+1 -1
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@@ -128,7 +128,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
assert(vue_slot != -1);
intrin->const_index[0] = vue_slot;
nir_src *vertex = nir_get_io_vertex_index_src(intrin);
nir_src *vertex = nir_get_io_arrayed_index_src(intrin);
if (vertex) {
if (nir_src_is_const(*vertex)) {
intrin->const_index[0] += nir_src_as_uint(*vertex) *