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intel/brw: Remove unused attrib workarounds

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
This commit is contained in:
Caio Oliveira
2024-02-23 15:20:29 -08:00
committed by Marge Bot
parent d3e451780b
commit 5a3f65e678
7 changed files with 4 additions and 170 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/compiler/brw_compile_vs.cpp
View File

@@ -31,7 +31,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
prog_data->inputs_read = nir->info.inputs_read;
prog_data->double_inputs_read = nir->info.vs.double_inputs;
brw_nir_lower_vs_inputs(nir, params->edgeflag_is_last, key->gl_attrib_wa_flags);
brw_nir_lower_vs_inputs(nir, params->edgeflag_is_last);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, debug_enabled,
key->base.robust_flags);

27
src/intel/compiler/brw_compiler.h
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@@ -259,17 +259,6 @@ struct brw_base_prog_key {
struct brw_sampler_prog_key_data tex;
};
/**
* The VF can't natively handle certain types of attributes, such as GL_FIXED
* or most 10_10_10_2 types. These flags enable various VS workarounds to
* "fix" attributes at the beginning of shaders.
*/
#define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
#define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
#define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
#define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
#define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
/**
* OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
* [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
@@ -308,20 +297,6 @@ struct brw_base_prog_key {
struct brw_vs_prog_key {
struct brw_base_prog_key base;
/**
* Per-attribute workaround flags
*
* For each attribute, a combination of BRW_ATTRIB_WA_*.
*
* For OpenGL, where we expose a maximum of 16 user input attributes
* we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
* slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
* expose up to 28 user input vertex attributes that are mapped to slots
* starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
* enough to hold this many slots.
*/
uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB, MAX_VK_VERT_ATTRIB)];
/**
* For pre-Gfx6 hardware, a bitfield indicating which texture coordinates
* are going to be replaced with point coordinates (as a consequence of a
@@ -346,7 +321,7 @@ struct brw_vs_prog_key {
*/
unsigned nr_userclip_plane_consts:4;
uint32_t padding: 25;
uint32_t padding:17;
};
/** The program key for Tessellation Control Shaders. */

4
src/intel/compiler/brw_debug_recompile.c
View File

@@ -91,10 +91,6 @@ debug_vs_recompile(const struct brw_compiler *c, void *log,
{
bool found = debug_base_recompile(c, log, &old_key->base, &key->base);
for (unsigned i = 0; i < VERT_ATTRIB_MAX; i++) {
found |= check("vertex attrib w/a flags", gl_attrib_wa_flags[i]);
}
found |= check("legacy user clipping", nr_userclip_plane_consts);
found |= check("copy edgeflag", copy_edgeflag);
found |= check("pointcoord replace", point_coord_replace);

5
src/intel/compiler/brw_nir.c
View File

@@ -344,8 +344,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
void
brw_nir_lower_vs_inputs(nir_shader *nir,
bool edgeflag_is_last,
const uint8_t *vs_attrib_wa_flags)
bool edgeflag_is_last)
{
/* Start with the location of the variable's base. */
nir_foreach_shader_in_variable(var, nir)
@@ -363,8 +362,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
brw_nir_apply_attribute_workarounds(nir, vs_attrib_wa_flags);
/* The last step is to remap VERT_ATTRIB_* to actual registers */
/* Whether or not we have any system generated values. gl_DrawID is not

3
src/intel/compiler/brw_nir.h
View File

@@ -152,8 +152,7 @@ bool brw_nir_lower_alpha_to_coverage(nir_shader *shader,
const struct brw_wm_prog_key *key,
const struct brw_wm_prog_data *prog_data);
void brw_nir_lower_vs_inputs(nir_shader *nir,
bool edgeflag_is_last,
const uint8_t *vs_attrib_wa_flags);
bool edgeflag_is_last);
void brw_nir_lower_vue_inputs(nir_shader *nir,
const struct intel_vue_map *vue_map);
void brw_nir_lower_tes_inputs(nir_shader *nir, const struct intel_vue_map *vue);

132
src/intel/compiler/brw_nir_attribute_workarounds.c
View File

@@ -1,132 +0,0 @@
/*
* Copyright © 2016 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "compiler/nir/nir_builder.h"
#include "brw_nir.h"
/**
* Prior to Haswell, the hardware can't natively support GL_FIXED or
* 2_10_10_10_REV vertex formats. This pass inserts extra shader code
* to produce the correct values.
*/
static bool
apply_attr_wa_instr(nir_builder *b, nir_instr *instr, void *cb_data)
{
const uint8_t *attrib_wa_flags = cb_data;
if (instr->type != nir_instr_type_intrinsic)
return false;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
if (intrin->intrinsic != nir_intrinsic_load_input)
return false;
uint8_t wa_flags = attrib_wa_flags[nir_intrinsic_base(intrin)];
if (wa_flags == 0)
return false;
b->cursor = nir_after_instr(instr);
nir_def *val = &intrin->def;
/* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
* come in as floating point conversions of the integer values.
*/
if (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK) {
nir_def *scaled =
nir_fmul_imm(b, val, 1.0f / 65536.0f);
nir_def *comps[4];
for (int i = 0; i < val->num_components; i++) {
bool rescale = i < (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK);
comps[i] = nir_channel(b, rescale ? scaled : val, i);
}
val = nir_vec(b, comps, val->num_components);
}
/* Do sign recovery for 2101010 formats if required. */
if (wa_flags & BRW_ATTRIB_WA_SIGN) {
/* sign recovery shift: <22, 22, 22, 30> */
nir_def *shift = nir_imm_ivec4(b, 22, 22, 22, 30);
val = nir_ishr(b, nir_ishl(b, val, shift), shift);
}
/* Apply BGRA swizzle if required. */
if (wa_flags & BRW_ATTRIB_WA_BGRA) {
val = nir_swizzle(b, val, (unsigned[4]){2,1,0,3}, 4);
}
if (wa_flags & BRW_ATTRIB_WA_NORMALIZE) {
/* ES 3.0 has different rules for converting signed normalized
* fixed-point numbers than desktop GL.
*/
if (wa_flags & BRW_ATTRIB_WA_SIGN) {
/* According to equation 2.2 of the ES 3.0 specification,
* signed normalization conversion is done by:
*
* f = c / (2^(b-1)-1)
*
* OpenGL 4.2+ uses this equation as well. Since most contexts
* promote to the new higher version, and this is what Haswell+
* hardware does anyway, we just always use this formula.
*/
nir_def *es3_normalize_factor =
nir_imm_vec4(b, 1.0f / ((1 << 9) - 1), 1.0f / ((1 << 9) - 1),
1.0f / ((1 << 9) - 1), 1.0f / ((1 << 1) - 1));
val = nir_fmax(b,
nir_fmul(b, nir_i2f32(b, val), es3_normalize_factor),
nir_imm_float(b, -1.0f));
} else {
/* The following equation is from the OpenGL 3.2 specification:
*
* 2.1 unsigned normalization
* f = c/(2^n-1)
*/
nir_def *normalize_factor =
nir_imm_vec4(b, 1.0f / ((1 << 10) - 1), 1.0f / ((1 << 10) - 1),
1.0f / ((1 << 10) - 1), 1.0f / ((1 << 2) - 1));
val = nir_fmul(b, nir_u2f32(b, val), normalize_factor);
}
}
if (wa_flags & BRW_ATTRIB_WA_SCALE) {
val = (wa_flags & BRW_ATTRIB_WA_SIGN) ? nir_i2f32(b, val)
: nir_u2f32(b, val);
}
nir_def_rewrite_uses_after(&intrin->def, val,
val->parent_instr);
return true;
}
bool
brw_nir_apply_attribute_workarounds(nir_shader *shader,
const uint8_t *attrib_wa_flags)
{
return nir_shader_instructions_pass(shader, apply_attr_wa_instr,
nir_metadata_block_index |
nir_metadata_dominance,
(void *)attrib_wa_flags);
}

1
src/intel/compiler/meson.build
View File

@@ -101,7 +101,6 @@ libintel_compiler_brw_files = files(
'brw_nir.h',
'brw_nir.c',
'brw_nir_analyze_ubo_ranges.c',
'brw_nir_attribute_workarounds.c',
'brw_nir_lower_cooperative_matrix.c',
'brw_nir_lower_cs_intrinsics.c',
'brw_nir_lower_alpha_to_coverage.c',