freedreno: Don't stomp VSC registers

These registers are shared between BR and BV. This means they can only
be written in BV or in BR during a special "disable binning" section
which synchronizes BR and BV. The register stomping infrastructure isn't
aware of this, so disable stomping for VSC.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37722>

src/freedreno/common/freedreno_stompable_regs.h

@@ -63,6 +63,15 @@ fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
       case REG_A7XX_SP_CS_VGS_CNTL:
          return false;
       }
+
+      /* The reg stomper doesn't play well with VSC registers because they are
+       * shared between BR and BV and it isn't part of the synchronization
+       * dance to enable BV and binning in BR with concurrent binning disabled
+       * to share the use of them.
+       */
+      if (reg >= REG_A6XX_VSC_BIN_SIZE && reg <= REG_A7XX_VSC_UNKNOWN_0D08)
+         return false;
+
       break;
    }
    default: {