r600/sfn: Update state docu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7142>
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@@ -4,16 +4,19 @@ This code is an attempt to implement a NIR backend for r600.
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## State
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piglits glsl-1.10 - 3.3 and gl-1.* gl-2.* and gl-3.* pass mostly like with TGSI, there are some fixes but
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also a few regressions.
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piglits gpu passes mostly like with TGSI, there are some fixes but also a few regressions.
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CTS gles
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- 2 passes like with TGSI
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- 3 no regressions, a few fixes compared to TGSI
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- 31
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* a few fixes with interpolation specifiers
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* a few regressiones with seperate_shader.random
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* syncronization has some unstable tests, this might be because global syncronization is missing (in both)
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## Currently missing features w.r.t. TGSI:
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- Tesselation shaders
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- compute shader support
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- image load/store
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- work group shared values
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- SSBO atomics
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- struct support
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## Needed optimizations:
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@@ -33,37 +36,13 @@ also a few regressions.
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## Problems
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- figure out what is wrong with the textcoord semantics: disabling it results in
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varyings beyond the supporteed VAR31, and enabling it lets some shaders with
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VAR0 fail.
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- UBOs have a strange behaviour: with
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glsl-1.50/uniform_buffer/gs-mat4x3.shader_test
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on TGSI we have
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ADD TEMP[1].xyz = CONST[1][0].xyzz CONST[1][1].xyzz
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with NIR we have
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vec4 ssa_12 = intrinsic load_ubo(_r600) (0, 0)(0 , 4 ,0)
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vec4 ssa_13 = intrinsic load_ubo(_r600) (0, 1)(0 , 4 ,0)
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vec3 ssa_14 = fadd ssa_12.xyw, ssa_13.xyw
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so why is the "w" component emitted?
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## Unknows
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- multi-function shaders, how to deal with them? fp64 seems to have lots
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of them, one option is to inline them
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- can type information from variables be harvested?
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lowering passes in NIR:
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- TESS IO address evaluation should be lowered
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- struct IO is not lowered. lower_io would need a rewrite of most IO in
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VS, GS, and FS
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- fp64 needs additional lowering to replace load, split and merge with vec2 ops
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nir_to_tgsi has some stuff there
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## Work plan
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The idea is to create two conversions: a NIR to a new R600 IR that
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can be used to run some finalizing optimizations (replacing the
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need for r600/sb) and the binary code generation.
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The implementation uses C++ to separate the code for the different
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shader types and the byte code generation backends. The initial attempt
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will use the already available r600_asm code
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