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freedreno/regs: Add 2 new a7xx modes to CP_COND_REG_EXEC

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Also reworked how CP_COND_REG_EXEC is defined to print
less irrelevant fields.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
This commit is contained in:
Danylo Piliaiev
2023-07-05 16:08:54 +02:00
committed by Marge Bot
parent 27312eb386
commit 5928ac6b64
8 changed files with 87 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+14 -14
View File
@@ -2279,7 +2279,7 @@ got cmdszdw=83
00000001002232a4: 0000: 70e30001 00000000
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 54 }
0000000100227000: 0000: 70c70002 34000000 00000036
opcode: CP_EVENT_WRITE (46) (2 dwords)
@@ -2398,7 +2398,7 @@ got cmdszdw=83
+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
00000001002270dc: 0000: 70460001 0000001e
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM | SYSMEM }
{ DWORDS = 4 }
0000000100227200: 0000: 70c70002 3c000000 00000004
opcode: CP_REG_WRITE (6d) (4 dwords)
@@ -3012,11 +3012,11 @@ got cmdszdw=83
00000001002232bc: 0000: 70bf8003 00208000 00000001 00000061
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 23 }
0000000100227238: 0000: 70c70002 34000000 00000017
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 17 }
0000000100227250: 0000: 70c70002 10000000 00000011
opcode: CP_EVENT_WRITE (46) (2 dwords)
@@ -3037,7 +3037,7 @@ got cmdszdw=83
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
0000000100227298: 0000: 70460001 0000001e
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 20 }
00000001002272a0: 0000: 70c70002 34000000 00000014
opcode: CP_EVENT_WRITE (46) (2 dwords)
@@ -3059,7 +3059,7 @@ got cmdszdw=83
!+ 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
00000001002272f4: 0000: 70460001 0000001e
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | SYSMEM }
{ DWORDS = 34 }
00000001002272fc: 0000: 70c70002 38000000 00000022
opcode: CP_BLIT (2c) (2 dwords)
@@ -3095,7 +3095,7 @@ got cmdszdw=83
event PC_CCU_INVALIDATE_COLOR
0000000100227388: 0000: 70460001 00000019
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM | SYSMEM }
{ DWORDS = 4 }
00000001002274ac: 0000: 70c70002 3c000000 00000004
opcode: CP_REG_WRITE (6d) (4 dwords)
@@ -3726,11 +3726,11 @@ got cmdszdw=83
00000001002232dc: 0000: 70bf8003 0020f000 00000001 00000061
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 23 }
000000010022750c: 0000: 70c70002 34000000 00000017
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 17 }
0000000100227524: 0000: 70c70002 10000000 00000011
opcode: CP_EVENT_WRITE (46) (2 dwords)
@@ -3751,7 +3751,7 @@ got cmdszdw=83
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
000000010022756c: 0000: 70460001 0000001e
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 20 }
0000000100227574: 0000: 70c70002 34000000 00000014
opcode: CP_EVENT_WRITE (46) (2 dwords)
@@ -3773,7 +3773,7 @@ got cmdszdw=83
!+ 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
00000001002275c8: 0000: 70460001 0000001e
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | SYSMEM }
{ DWORDS = 34 }
00000001002275d0: 0000: 70c70002 38000000 00000022
opcode: CP_BLIT (2c) (2 dwords)
@@ -3809,7 +3809,7 @@ got cmdszdw=83
event PC_CCU_INVALIDATE_COLOR
000000010022765c: 0000: 70460001 00000019
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM | SYSMEM }
{ DWORDS = 4 }
0000000100227780: 0000: 70c70002 3c000000 00000004
opcode: CP_REG_WRITE (6d) (4 dwords)
@@ -4452,11 +4452,11 @@ ESTIMATED CRASH LOCATION!
00000001002232fc: 0000: 70bf8003 00216000 00000001 00000061
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 3 }
00000001002277fc: 0000: 70c70002 34000000 00000003
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM | SYSMEM }
{ DWORDS = 4 }
0000000100227930: 0000: 70c70002 3c000000 00000004
opcode: CP_REG_WRITE (6d) (4 dwords)
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+3 -3
View File
@@ -435,7 +435,7 @@ cmdstream[0]: 265 dwords
ibaddr:000000000115e000
ibsize:000000f1
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM }
{ DWORDS = 23 }
000000000115e000: 0000: 70c70002 34000000 00000017
write RB_BLIT_SCISSOR_TL (88d1)
@@ -495,7 +495,7 @@ cmdstream[0]: 265 dwords
RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
000000000115e05c: 0000: 4888d102 00000000 00ff00ff
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | SYSMEM }
{ DWORDS = 0 }
000000000115e068: 0000: 70c70002 38000000 00000000
write RB_DEPTH_BUFFER_INFO (8872)
@@ -555,7 +555,7 @@ cmdstream[0]: 265 dwords
RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
000000000115e128: 0000: 4088d501 00000000
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
{ MODE = RENDER_MODE | GMEM | SYSMEM }
{ DWORDS = 4 }
000000000115e130: 0000: 70c70002 3c000000 00000004
opcode: CP_REG_WRITE (6d) (4 dwords)
src/freedreno/.gitlab-ci/reference/fd-clouds.log
+11 -11
View File
@@ -1476,7 +1476,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d918f0: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 7 }
0000000001d918f8: 0000: 70c70002 10000000 00000007
opcode: CP_REG_TO_MEM (3e) (4 dwords)
@@ -1560,7 +1560,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d919d8: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 11 }
0000000001d919e0: 0000: 70c70002 10000000 0000000b
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
@@ -1710,7 +1710,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0xc38 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91aac: 0000: 70b90001 02000c38
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 4 }
0000000001d91ab4: 0000: 70c70002 10000000 00000004
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
@@ -6752,7 +6752,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91adc: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 2 }
0000000001d91ae4: 0000: 70c70002 10000000 00000002
opcode: CP_SET_MARKER (65) (2 dwords)
@@ -6877,7 +6877,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91ba4: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 11 }
0000000001d91bac: 0000: 70c70002 10000000 0000000b
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
@@ -6951,7 +6951,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0xc39 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91c78: 0000: 70b90001 02000c39
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 4 }
0000000001d91c80: 0000: 70c70002 10000000 00000004
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
@@ -6968,7 +6968,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91ca8: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 2 }
0000000001d91cb0: 0000: 70c70002 10000000 00000002
opcode: CP_SET_MARKER (65) (2 dwords)
@@ -7046,7 +7046,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91d70: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 11 }
0000000001d91d78: 0000: 70c70002 10000000 0000000b
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
@@ -7120,7 +7120,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0xc3a | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91e44: 0000: 70b90001 02000c3a
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 4 }
0000000001d91e4c: 0000: 70c70002 10000000 00000004
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
@@ -7137,7 +7137,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91e74: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 2 }
0000000001d91e7c: 0000: 70c70002 10000000 00000002
opcode: CP_SET_MARKER (65) (2 dwords)
@@ -7215,7 +7215,7 @@ cmdstream[0]: 1023 dwords
{ SOURCE = SOURCE_REG | REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME | PRED_BIT = 0 }
0000000001d91f3c: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
{ MODE = PRED_TEST | PRED_BIT = 0 }
{ DWORDS = 11 }
0000000001d91f44: 0000: 70c70002 10000000 0000000b
opcode: CP_SET_BIN_DATA5 (2f) (8 dwords)
src/freedreno/registers/adreno/adreno_pm4.xml
+50 -10
View File
@@ -1823,12 +1823,19 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<value value="2" name="REG_COMPARE"/>
<!-- test if certain render modes are set via CP_SET_MARKER -->
<value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
<!-- compare REG0 for equality with immediate -->
<value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/>
<!-- test which of BR/BV are enabled -->
<value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="REG0" low="0" high="17" type="hex"/>
<reg32 offset="0" name="0" varset="compare_mode">
<bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/>
<!-- the predicate bit to test (new in gen3+) -->
<bitfield name="PRED_BIT" low="18" high="22" varset="chip" variants="A6XX-" type="uint"/>
<bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/>
<bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/>
<!-- With REG_COMPARE instead of register read from ONCHIP memory -->
<bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
<!--
Note: these bits have the same meaning, and use the same
@@ -1838,19 +1845,52 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
-->
<!-- RM6_BINNING -->
<bitfield name="BINNING" pos="25" varset="chip" variants="A6XX-" type="boolean"/>
<bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
<!-- all others -->
<bitfield name="GMEM" pos="26" varset="chip" variants="A6XX-" type="boolean"/>
<bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
<!-- RM6_BYPASS -->
<bitfield name="SYSMEM" pos="27" varset="chip" variants="A6XX-" type="boolean"/>
<bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
<bitfield name="MODE" low="28" high="31" type="compare_mode"/>
<bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
<bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/>
<bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/>
</reg32>
<!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
<stripe varset="compare_mode" variants="PRED_TEST">
<reg32 offset="1" name="1">
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
</reg32>
</stripe>
<reg32 offset="1" name="1">
<bitfield name="DWORDS" low="0" high="31" type="uint"/>
<stripe varset="compare_mode" variants="REG_COMPARE">
<reg32 offset="1" name="1">
<bitfield name="REG1" low="0" high="17" type="hex"/>
<!-- Instead of register read from ONCHIP memory -->
<bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
</reg32>
</stripe>
<stripe varset="compare_mode" variants="RENDER_MODE">
<reg32 offset="1" name="1">
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
</reg32>
</stripe>
<stripe varset="compare_mode" variants="REG_COMPARE_IMM">
<reg32 offset="1" name="1">
<bitfield name="IMM" low="0" high="31"/>
</reg32>
</stripe>
<stripe varset="compare_mode" variants="THREAD_MODE">
<reg32 offset="1" name="1">
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
</reg32>
</stripe>
<reg32 offset="2" name="2">
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
</reg32>
</domain>
src/freedreno/vulkan/tu_cmd_buffer.cc
+1 -1
View File
@@ -452,7 +452,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(4));
}
tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
src/freedreno/vulkan/tu_cs.cc
+1 -1
View File
@@ -445,7 +445,7 @@ tu_cs_reserve_space(struct tu_cs *cs, uint32_t reserved_size)
cs->cond_dwords[i] = cs->cur;
/* Emit dummy DWORD field here */
tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(0));
tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(0));
}
/* double the size for the next bo, also there is an upper
src/freedreno/vulkan/tu_cs.h
+6 -1
View File
@@ -442,6 +442,11 @@ tu_cond_exec_start(struct tu_cs *cs, uint32_t cond_flags)
assert(cs->mode == TU_CS_MODE_GROW);
assert(cs->cond_stack_depth < TU_COND_EXEC_STACK_SIZE);
ASSERTED enum compare_mode mode =
(enum compare_mode)((cond_flags & CP_COND_REG_EXEC_0_MODE__MASK) >>
CP_COND_REG_EXEC_0_MODE__SHIFT);
assert(mode == PRED_TEST || mode == RENDER_MODE || mode == THREAD_MODE);
tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
tu_cs_emit(cs, cond_flags);
@@ -449,7 +454,7 @@ tu_cond_exec_start(struct tu_cs *cs, uint32_t cond_flags)
cs->cond_dwords[cs->cond_stack_depth] = cs->cur;
/* Emit dummy DWORD field here */
tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(0));
tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(0));
cs->cond_stack_depth++;
}
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+1 -1
View File
@@ -770,7 +770,7 @@ emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count));
OUT_RING(ring, PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(4 * count));
for (unsigned i = 0; i < count; i++) {
uint32_t dwords;