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aco: Implement new Geometry Shader intrinsics.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
This commit is contained in:
Timur Kristóf
2021-02-22 20:18:08 +01:00
committed by Marge Bot
parent 5c95b32c6e
commit 582229585b
2 changed files with 21 additions and 0 deletions
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src/amd/compiler/aco_instruction_selection.cpp
+18
View File
@@ -8175,6 +8175,9 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.vs_rel_patch_id));
break;
} else if (ctx->stage.hw == HWStage::GS || ctx->stage.hw == HWStage::NGG) {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), thread_id_in_threadgroup(ctx));
break;
}
Temp id = emit_mbcnt(ctx, bld.tmp(v1));
@@ -8787,6 +8790,21 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.tess_offchip_offset));
break;
}
case nir_intrinsic_load_ring_esgs_amd: {
unsigned ring = ctx->stage.hw == HWStage::ES ? RING_ESGS_VS : RING_ESGS_GS;
bld.smem(aco_opcode::s_load_dwordx4, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
ctx->program->private_segment_buffer, Operand(ring * 16u));
break;
}
case nir_intrinsic_load_ring_es2gs_offset_amd: {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.es2gs_offset));
break;
}
case nir_intrinsic_load_gs_vertex_offset_amd: {
unsigned b = nir_intrinsic_base(instr);
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.gs_vtx_offset[b]));
break;
}
default:
isel_err(&instr->instr, "Unimplemented intrinsic instr");
abort();
src/amd/compiler/aco_instruction_selection_setup.cpp
+3
View File
@@ -782,6 +782,8 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_intrinsic_load_ring_tess_factors_offset_amd:
case nir_intrinsic_load_ring_tess_offchip_amd:
case nir_intrinsic_load_ring_tess_offchip_offset_amd:
case nir_intrinsic_load_ring_esgs_amd:
case nir_intrinsic_load_ring_es2gs_offset_amd:
type = RegType::sgpr;
break;
case nir_intrinsic_load_sample_id:
@@ -858,6 +860,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_intrinsic_load_primitive_id:
case nir_intrinsic_load_buffer_amd:
case nir_intrinsic_load_tess_rel_patch_id_amd:
case nir_intrinsic_load_gs_vertex_offset_amd:
type = RegType::vgpr;
break;
case nir_intrinsic_shuffle: