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gallium/radeon: remove old_fence parameter from r600_gfx_write_event_eop

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just use the new scratch buffer.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-08-15 02:50:22 +02:00
parent 41e053954d
commit 57fb1bb585
5 changed files with 17 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeon/r600_pipe_common.c
+11 -4
View File
@@ -103,8 +103,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
unsigned event, unsigned event_flags,
unsigned data_sel,
struct r600_resource *buf, uint64_t va,
uint32_t old_fence, uint32_t new_fence,
unsigned query_type)
uint32_t new_fence, unsigned query_type)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
unsigned op = EVENT_TYPE(event) |
@@ -146,6 +145,9 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
} else {
if (ctx->chip_class == CIK ||
ctx->chip_class == VI) {
struct r600_resource *scratch = ctx->eop_bug_scratch;
uint64_t va = scratch->gpu_address;
/* Two EOP events are required to make all engines go idle
* (and optional cache flushes executed) before the timestamp
* is written.
@@ -154,8 +156,11 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
radeon_emit(cs, op);
radeon_emit(cs, va);
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
radeon_emit(cs, old_fence); /* immediate data */
radeon_emit(cs, 0); /* immediate data */
radeon_emit(cs, 0); /* unused */
radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
@@ -679,7 +684,9 @@ bool r600_common_context_init(struct r600_common_context *rctx,
r600_query_init(rctx);
cayman_init_msaa(&rctx->b);
if (rctx->chip_class == GFX9) {
if (rctx->chip_class == CIK ||
rctx->chip_class == VI ||
rctx->chip_class == GFX9) {
rctx->eop_bug_scratch = (struct r600_resource*)
pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * rscreen->info.num_render_backends);
src/gallium/drivers/radeon/r600_pipe_common.h
+1 -2
View File
@@ -748,8 +748,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
unsigned event, unsigned event_flags,
unsigned data_sel,
struct r600_resource *buf, uint64_t va,
uint32_t old_fence, uint32_t new_fence,
unsigned query_type);
uint32_t new_fence, unsigned query_type);
unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
void r600_gfx_wait_fence(struct r600_common_context *ctx,
uint64_t va, uint32_t ref, uint32_t mask);
src/gallium/drivers/radeon/r600_query.c
+3 -3
View File
@@ -780,7 +780,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
* (bottom-of-pipe)
*/
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
0, 3, NULL, va, 0, 0, query->b.type);
0, 3, NULL, va, 0, query->b.type);
}
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
@@ -865,7 +865,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
/* fall through */
case PIPE_QUERY_TIMESTAMP:
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
0, 3, NULL, va, 0, 0, query->b.type);
0, 3, NULL, va, 0, query->b.type);
fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
@@ -888,7 +888,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
if (fence_va)
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
query->buffer.buf, fence_va, 0, 0x80000000,
query->buffer.buf, fence_va, 0x80000000,
query->b.type);
}
src/gallium/drivers/radeonsi/si_perfcounter.c
+1 -1
View File
@@ -591,7 +591,7 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
struct radeon_winsys_cs *cs = ctx->gfx.cs;
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
buffer, va, 1, 0, 0);
buffer, va, 0, 0);
r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
src/gallium/drivers/radeonsi/si_state_draw.c
+1 -2
View File
@@ -894,7 +894,7 @@ void si_emit_cache_flush(struct si_context *sctx)
/* Necessary for DCC */
if (rctx->chip_class == VI)
r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0, 0, NULL, 0, 0, 0, 0);
0, 0, NULL, 0, 0, 0);
}
if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
@@ -995,7 +995,6 @@ void si_emit_cache_flush(struct si_context *sctx)
r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
sctx->wait_mem_scratch, va,
sctx->wait_mem_number - 1,
sctx->wait_mem_number, 0);
r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
}