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ac/nir: remove unnecessary 16-bit handling from pre-rast GS and XFB loads/stores

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All callers always pass 32 bits in there.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35473>
This commit is contained in:
Marek Olšák
2025-06-01 21:16:13 -04:00
committed by Marge Bot
parent 65972f2301
commit 56f80479fc
5 changed files with 28 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/nir/ac_nir_create_gs_copy_shader.c
+2 -2
View File
@@ -45,7 +45,7 @@ ac_nir_create_gs_copy_shader(const nir_shader *gs_nir, ac_nir_lower_legacy_gs_op
continue;
if (ac_nir_is_const_output(out, i, j)) {
out->outputs[i][j] = ac_nir_get_const_output(&b, 32, out, i, j);
out->outputs[i][j] = ac_nir_get_const_output(&b, out, i, j);
continue;
}
@@ -72,7 +72,7 @@ ac_nir_create_gs_copy_shader(const nir_shader *gs_nir, ac_nir_lower_legacy_gs_op
nir_def *load_val;
if (ac_nir_is_const_output(out, VARYING_SLOT_VAR0_16BIT + i, j)) {
load_val = ac_nir_get_const_output(&b, 32, out, i, j);
load_val = ac_nir_get_const_output(&b, out, i, j);
} else {
unsigned base = offset * gs_nir->info.gs.vertices_out * 16;
load_val = nir_load_buffer_amd(&b, 1, 32, gsvs_ring, vtx_offset, zero, zero,
src/amd/common/nir/ac_nir_helpers.h
+3 -3
View File
@@ -242,7 +242,7 @@ bool
ac_nir_is_const_output(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigned component);
nir_def *
ac_nir_get_const_output(nir_builder *b, unsigned bit_size, ac_nir_prerast_out *pr_out, gl_varying_slot slot,
ac_nir_get_const_output(nir_builder *b, ac_nir_prerast_out *pr_out, gl_varying_slot slot,
unsigned component);
void
@@ -250,7 +250,7 @@ ac_nir_store_shared_xfb(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_nir_
gl_varying_slot slot, unsigned component);
nir_def *
ac_nir_load_shared_xfb(nir_builder *b, unsigned bit_size, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
ac_nir_load_shared_xfb(nir_builder *b, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
gl_varying_slot slot, unsigned component);
void
@@ -258,7 +258,7 @@ ac_nir_store_shared_gs_out(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_n
gl_varying_slot slot, unsigned component);
nir_def *
ac_nir_load_shared_gs_out(nir_builder *b, unsigned bit_size, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
ac_nir_load_shared_gs_out(nir_builder *b, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
gl_varying_slot slot, unsigned component);
void
src/amd/common/nir/ac_nir_lower_ngg.c
+1 -1
View File
@@ -209,7 +209,7 @@ emit_ngg_nogs_prim_export(nir_builder *b, lower_ngg_nogs_state *s, nir_def *arg)
nir_def *vtx_idx = nir_load_var(b, s->gs_vtx_indices_vars[i]);
nir_def *addr = pervertex_lds_addr(b, s, vtx_idx, s->pervertex_lds_bytes);
/* Edge flags share LDS with XFB. */
nir_def *edge = ac_nir_load_shared_xfb(b, 32, addr, &s->out, VARYING_SLOT_EDGE, 0);
nir_def *edge = ac_nir_load_shared_xfb(b, addr, &s->out, VARYING_SLOT_EDGE, 0);
if (s->options->hw_info->gfx_level >= GFX12)
mask = nir_ior(b, mask, nir_ishl_imm(b, edge, 8 + i * 9));
src/amd/common/nir/ac_nir_lower_ngg_gs.c
+5 -5
View File
@@ -349,7 +349,7 @@ ngg_gs_process_out_vertex(nir_builder *b, nir_def *out_vtx_lds_addr, lower_ngg_g
unsigned mask = ac_nir_gs_output_component_mask_with_stream(&s->out.infos[slot], 0);
u_foreach_bit(c, mask) {
s->out.outputs[slot][c] = ac_nir_load_shared_gs_out(b, 32, exported_out_vtx_lds_addr,
s->out.outputs[slot][c] = ac_nir_load_shared_gs_out(b, exported_out_vtx_lds_addr,
&s->out, slot, c);
}
}
@@ -361,7 +361,7 @@ ngg_gs_process_out_vertex(nir_builder *b, nir_def *out_vtx_lds_addr, lower_ngg_g
unsigned mask = mask_lo | mask_hi;
u_foreach_bit(c, mask) {
nir_def *load_val = ac_nir_load_shared_gs_out(b, 32, exported_out_vtx_lds_addr,
nir_def *load_val = ac_nir_load_shared_gs_out(b, exported_out_vtx_lds_addr,
&s->out, VARYING_SLOT_VAR0_16BIT + i, c);
if (mask_lo & BITFIELD_BIT(c))
@@ -575,7 +575,7 @@ ngg_gs_cull_primitive(nir_builder *b, nir_def *tid_in_tg, nir_def *max_vtxcnt,
for (unsigned i = 0; i < s->num_vertices_per_primitive; i++) {
/* Load X, Y, W position components. Z is loaded only if we clip against POS. */
for (unsigned c = 0; c < 4; c == 1 && !clip_against_pos ? c += 2 : c++)
pos[i][c] = ac_nir_load_shared_gs_out(b, 32, vtxptr[i], &s->out, VARYING_SLOT_POS, c);
pos[i][c] = ac_nir_load_shared_gs_out(b, vtxptr[i], &s->out, VARYING_SLOT_POS, c);
}
nir_def *accepted_by_clipdist = nir_imm_true(b);
@@ -591,7 +591,7 @@ ngg_gs_cull_primitive(nir_builder *b, nir_def *tid_in_tg, nir_def *max_vtxcnt,
if (!clip_against_pos) {
for (unsigned i = 0; i < s->num_vertices_per_primitive; i++) {
for (unsigned c = 0; c < 4; c++) {
clipvertex[i][c] = ac_nir_load_shared_gs_out(b, 32, vtxptr[i], &s->out,
clipvertex[i][c] = ac_nir_load_shared_gs_out(b, vtxptr[i], &s->out,
VARYING_SLOT_CLIP_VERTEX, c);
}
}
@@ -610,7 +610,7 @@ ngg_gs_cull_primitive(nir_builder *b, nir_def *tid_in_tg, nir_def *max_vtxcnt,
/* Load clip distances. */
u_foreach_bit(c, s->options->cull_clipdist_mask) {
for (unsigned i = 0; i < s->num_vertices_per_primitive; i++) {
clipdist[i][c] = ac_nir_load_shared_gs_out(b, 32, vtxptr[i], &s->out,
clipdist[i][c] = ac_nir_load_shared_gs_out(b, vtxptr[i], &s->out,
VARYING_SLOT_CLIP_DIST0 + c / 4, c % 4);
}
}
src/amd/common/nir/ac_nir_prerast_utils.c
+17 -16
View File
@@ -1369,8 +1369,7 @@ ac_nir_get_lds_gs_out_slot_offset(ac_nir_prerast_out *pr_out, gl_varying_slot sl
}
static unsigned
ac_nir_ngg_get_xfb_lds_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigned component,
bool data_is_16bit)
ac_nir_ngg_get_xfb_lds_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigned component)
{
assert(component < 4);
unsigned lds_slot_offset = 0, lds_component_mask = 0;
@@ -1383,8 +1382,6 @@ ac_nir_ngg_get_xfb_lds_offset(ac_nir_prerast_out *pr_out, gl_varying_slot slot,
lds_slot_offset = pr_out->infos_16bit_lo[i].packed_slot_xfb_lds_offset;
lds_component_mask = pr_out->infos_16bit_lo[i].xfb_lds_components_mask |
pr_out->infos_16bit_hi[i].xfb_lds_components_mask;
} else if (data_is_16bit) {
assert(!"unimplemented");
} else {
lds_slot_offset = pr_out->infos[slot].packed_slot_xfb_lds_offset;
lds_component_mask = pr_out->infos[slot].xfb_lds_components_mask & ~pr_out->infos[slot].const_mask;
@@ -1406,16 +1403,16 @@ ac_nir_is_const_output(ac_nir_prerast_out *pr_out, gl_varying_slot slot, unsigne
}
nir_def *
ac_nir_get_const_output(nir_builder *b, unsigned bit_size, ac_nir_prerast_out *pr_out, gl_varying_slot slot,
ac_nir_get_const_output(nir_builder *b, ac_nir_prerast_out *pr_out, gl_varying_slot slot,
unsigned component)
{
if (!ac_nir_is_const_output(pr_out, slot, component))
return NULL;
if (slot >= VARYING_SLOT_VAR0_16BIT)
return nir_imm_intN_t(b, pr_out->const_values_16bit[slot - VARYING_SLOT_VAR0_16BIT][component], bit_size);
return nir_imm_intN_t(b, pr_out->const_values_16bit[slot - VARYING_SLOT_VAR0_16BIT][component], 32);
else
return nir_imm_intN_t(b, pr_out->const_values[slot][component], bit_size);
return nir_imm_intN_t(b, pr_out->const_values[slot][component], 32);
}
void
@@ -1423,23 +1420,25 @@ ac_nir_store_shared_xfb(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_nir_
gl_varying_slot slot, unsigned component)
{
assert(value->num_components == 1);
assert(value->bit_size == 32);
if (ac_nir_is_const_output(pr_out, slot, component))
return;
unsigned offset = ac_nir_ngg_get_xfb_lds_offset(pr_out, slot, component, value->bit_size == 16);
unsigned offset = ac_nir_ngg_get_xfb_lds_offset(pr_out, slot, component);
nir_store_shared(b, value, vtxptr, .base = offset, .align_mul = 4);
}
nir_def *
ac_nir_load_shared_xfb(nir_builder *b, unsigned bit_size, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
ac_nir_load_shared_xfb(nir_builder *b, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
gl_varying_slot slot, unsigned component)
{
nir_def *const_val = ac_nir_get_const_output(b, bit_size, pr_out, slot, component);
nir_def *const_val = ac_nir_get_const_output(b, pr_out, slot, component);
if (const_val)
return const_val;
unsigned offset = ac_nir_ngg_get_xfb_lds_offset(pr_out, slot, component, bit_size == 16);
return nir_load_shared(b, 1, bit_size, vtxptr, .base = offset, .align_mul = 4);
unsigned offset = ac_nir_ngg_get_xfb_lds_offset(pr_out, slot, component);
return nir_load_shared(b, 1, 32, vtxptr, .base = offset, .align_mul = 4);
}
void
@@ -1447,6 +1446,8 @@ ac_nir_store_shared_gs_out(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_n
gl_varying_slot slot, unsigned component)
{
assert(value->num_components == 1);
assert(value->bit_size == 32);
if (ac_nir_is_const_output(pr_out, slot, component))
return;
@@ -1455,15 +1456,15 @@ ac_nir_store_shared_gs_out(nir_builder *b, nir_def *value, nir_def *vtxptr, ac_n
}
nir_def *
ac_nir_load_shared_gs_out(nir_builder *b, unsigned bit_size, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
ac_nir_load_shared_gs_out(nir_builder *b, nir_def *vtxptr, ac_nir_prerast_out *pr_out,
gl_varying_slot slot, unsigned component)
{
nir_def *const_val = ac_nir_get_const_output(b, bit_size, pr_out, slot, component);
nir_def *const_val = ac_nir_get_const_output(b, pr_out, slot, component);
if (const_val)
return const_val;
unsigned offset = ac_nir_get_lds_gs_out_slot_offset(pr_out, slot, component);
return nir_load_shared(b, 1, bit_size, vtxptr, .base = offset, .align_mul = 4);
return nir_load_shared(b, 1, 32, vtxptr, .base = offset, .align_mul = 4);
}
void
@@ -1495,7 +1496,7 @@ ac_nir_ngg_build_streamout_vertex(nir_builder *b, nir_xfb_info *info,
unsigned count = util_bitcount(out->component_mask);
for (unsigned comp = 0; comp < count; comp++) {
nir_def *data = ac_nir_load_shared_xfb(b, 32, vtx_lds_addr, pr_out, out->location,
nir_def *data = ac_nir_load_shared_xfb(b, vtx_lds_addr, pr_out, out->location,
out->component_offset + comp);
/* Convert 16-bit outputs to 32-bit.