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Merge branch 'r345-cleanup' of git://people.freedesktop.org/~agd5f/mesa into r500test

Browse Source 
Adding Alex's cleanup patches. This adds r5xx TCL! Whoo-hoo!
Conflicts:

	src/mesa/drivers/dri/r300/r300_state.c
	src/mesa/drivers/dri/radeon/radeon_chipset.h
	src/mesa/drivers/dri/radeon/radeon_screen.c
This commit is contained in:
Corbin Simpson
2008-05-02 15:57:57 -07:00
parent 92a0e93ac3 1226aba119
commit 568d369d77
8 changed files with 478 additions and 135 deletions
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src/mesa/drivers/dri/r300/r300_cmdbuf.c
+22 -14
View File
@@ -328,12 +328,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1);
ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
cmdpacket0(R300_VAP_INPUT_ROUTE_0_0, 1);
cmdpacket0(R300_VAP_PROG_STREAM_CNTL_0, 1);
ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
cmdpacket0(R300_VAP_INPUT_ROUTE_1_0, 1);
cmdpacket0(R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_INPUT_CNTL_0, 2);
r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_VTX_STATE_CNTL, 2);
ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
@@ -481,27 +481,35 @@ void r300InitCmdBuf(r300ContextPtr r300)
int i;
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
r300->hw.vpi.cmd[R300_VPI_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_PROGRAM, 0);
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[R300_VPP_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_PARAMETERS, 0);
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[R300_VPS_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1);
cmdvpu(R300_PVS_CODE_START, 0);
if (is_r500) {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[R300_VPP_CMD_0] =
cmdvpu(R500_PVS_CONST_START, 0);
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[R300_VPS_CMD_0] =
cmdvpu(R500_POINT_VPORT_SCALE_OFFSET, 1);
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
cmdvpu(R500_PVS_UPLOAD_CLIP_PLANE0+i, 1);
cmdvpu(R500_PVS_UCP_START + i, 1);
}
} else {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[R300_VPP_CMD_0] =
cmdvpu(R300_PVS_CONST_START, 0);
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[R300_VPS_CMD_0] =
cmdvpu(R300_POINT_VPORT_SCALE_OFFSET, 1);
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_CLIP_PLANE0+i, 1);
cmdvpu(R300_PVS_UCP_START + i, 1);
}
}
}
src/mesa/drivers/dri/r300/r300_emit.c
+18 -10
View File
@@ -216,14 +216,18 @@ static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
for (i = 0; i < nr; i += 2) {
/* make sure input is valid, would lockup the gpu */
assert(inputs[tab[i]] != -1);
dw = R300_INPUT_ROUTE_FLOAT | (inputs[tab[i]] << 8) | (attribptr[tab[i]]->size - 1);
dw = (R300_SIGNED |
(inputs[tab[i]] << R300_DST_VEC_LOC_SHIFT) |
(attribptr[tab[i]]->size - 1)) << R300_DATA_TYPE_0_SHIFT;
if (i + 1 == nr) {
dw |= R300_VAP_INPUT_ROUTE_END;
dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
} else {
assert(inputs[tab[i + 1]] != -1);
dw |= (R300_INPUT_ROUTE_FLOAT | (inputs[tab[i + 1]] << 8) | (attribptr[tab[i + 1]]->size - 1)) << 16;
dw |= (R300_SIGNED |
(inputs[tab[i + 1]] << R300_DST_VEC_LOC_SHIFT) |
(attribptr[tab[i + 1]]->size - 1)) << R300_DATA_TYPE_1_SHIFT;
if (i + 2 == nr) {
dw |= (R300_VAP_INPUT_ROUTE_END << 16);
dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
}
}
dst[i >> 1] = dw;
@@ -234,10 +238,10 @@ static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
static GLuint r300VAPInputRoute1Swizzle(int swizzle[4])
{
return (swizzle[0] << R300_INPUT_ROUTE_X_SHIFT) |
(swizzle[1] << R300_INPUT_ROUTE_Y_SHIFT) |
(swizzle[2] << R300_INPUT_ROUTE_Z_SHIFT) |
(swizzle[3] << R300_INPUT_ROUTE_W_SHIFT);
return (swizzle[0] << R300_SWIZZLE_SELECT_X_SHIFT) |
(swizzle[1] << R300_SWIZZLE_SELECT_Y_SHIFT) |
(swizzle[2] << R300_SWIZZLE_SELECT_Z_SHIFT) |
(swizzle[3] << R300_SWIZZLE_SELECT_W_SHIFT);
}
GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
@@ -245,9 +249,13 @@ GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
GLuint i, dw;
for (i = 0; i < nr; i += 2) {
dw = r300VAPInputRoute1Swizzle(swizzle[i]) | R300_INPUT_ROUTE_ENABLE;
dw = (r300VAPInputRoute1Swizzle(swizzle[i]) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y |
R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT;
if (i + 1 < nr) {
dw |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) | R300_INPUT_ROUTE_ENABLE) << 16;
dw |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y |
R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT;
}
dst[i >> 1] = dw;
}
src/mesa/drivers/dri/r300/r300_ioctl.c
+23 -8
View File
@@ -204,11 +204,15 @@ static void r300EmitClearState(GLcontext * ctx)
* these registers, as well as the actual values used for rendering.
*/
R300_STATECHANGE(r300, vir[0]);
reg_start(R300_VAP_INPUT_ROUTE_0_0, 0);
reg_start(R300_VAP_PROG_STREAM_CNTL_0, 0);
if (!has_tcl)
e32(0x22030003);
/*e32(0x22030003);*/
e32(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
else
e32(0x21030003);
/*e32(0x21030003);*/
e32(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
/* disable fog */
R300_STATECHANGE(r300, fogs);
@@ -216,13 +220,24 @@ static void r300EmitClearState(GLcontext * ctx)
e32(0x0);
R300_STATECHANGE(r300, vir[1]);
reg_start(R300_VAP_INPUT_ROUTE_1_0, 0);
e32(0xF688F688);
reg_start(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0);
e32(((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
<< R300_SWIZZLE0_SHIFT) |
(((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
<< R300_SWIZZLE1_SHIFT)));
/* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
R300_STATECHANGE(r300, vic);
reg_start(R300_VAP_INPUT_CNTL_0, 1);
e32(R300_INPUT_CNTL_0_COLOR);
reg_start(R300_VAP_VTX_STATE_CNTL, 1);
e32((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
e32(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
R300_STATECHANGE(r300, vte);
@@ -268,7 +283,7 @@ static void r300EmitClearState(GLcontext * ctx)
if (has_tcl) {
R300_STATECHANGE(r300, vap_clip_cntl);
reg_start(R300_VAP_CLIP_CNTL, 0);
e32(R300_221C_CLEAR);
e32(R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
}
R300_STATECHANGE(r300, ps);
src/mesa/drivers/dri/r300/r300_reg.h
+124 -76
View File
@@ -70,6 +70,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* Stolen from r200 code from Christoph Brill (It's a guess!)
*/
#define R300_VAP_CNTL 0x2080
# define R300_PVS_NUM_SLOTS_SHIFT 0
# define R300_PVS_NUM_CNTLRS_SHIFT 4
# define R300_PVS_NUM_FPUS_SHIFT 8
# define R300_VF_MAX_VTX_NUM_SHIFT 18
# define R300_GL_CLIP_SPACE_DEF (0 << 22)
# define R300_DX_CLIP_SPACE_DEF (1 << 22)
# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
/* This register is written directly and also starts data section
* in many 3d CP_PACKET3's
@@ -125,24 +132,23 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT (1<<0)
# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT (1<<1)
# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS (1<<2)
# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS (1<<3)
# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS (1<<4)
# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0
# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1
# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2
# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3
# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
#define R300_SE_VTE_CNTL 0x20b0
# define R300_VPORT_X_SCALE_ENA 0x00000001
# define R300_VPORT_X_OFFSET_ENA 0x00000002
# define R300_VPORT_Y_SCALE_ENA 0x00000004
# define R300_VPORT_Y_OFFSET_ENA 0x00000008
# define R300_VPORT_Z_SCALE_ENA 0x00000010
# define R300_VPORT_Z_OFFSET_ENA 0x00000020
# define R300_VTX_XY_FMT 0x00000100
# define R300_VTX_Z_FMT 0x00000200
# define R300_VTX_W0_FMT 0x00000400
# define R300_VTX_W0_NORMALIZE 0x00000800
# define R300_VTX_ST_DENORMALIZED 0x00001000
# define R300_VPORT_X_SCALE_ENA (1 << 0)
# define R300_VPORT_X_OFFSET_ENA (1 << 1)
# define R300_VPORT_Y_SCALE_ENA (1 << 2)
# define R300_VPORT_Y_OFFSET_ENA (1 << 3)
# define R300_VPORT_Z_SCALE_ENA (1 << 4)
# define R300_VPORT_Z_OFFSET_ENA (1 << 5)
# define R300_VTX_XY_FMT (1 << 8)
# define R300_VTX_Z_FMT (1 << 9)
# define R300_VTX_W0_FMT (1 << 10)
# define R300_SERIAL_PROC_ENA (1 << 11)
/* BEGIN: Vertex data assembly - lots of uncertainties */
@@ -211,27 +217,31 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* Always set COMPONENTS_4 in immediate mode.
*/
#define R300_VAP_INPUT_ROUTE_0_0 0x2150
# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
# define R300_VAP_INPUT_ROUTE_END (1 << 13)
# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
#define R300_VAP_INPUT_ROUTE_0_1 0x2154
#define R300_VAP_INPUT_ROUTE_0_2 0x2158
#define R300_VAP_INPUT_ROUTE_0_3 0x215C
#define R300_VAP_INPUT_ROUTE_0_4 0x2160
#define R300_VAP_INPUT_ROUTE_0_5 0x2164
#define R300_VAP_INPUT_ROUTE_0_6 0x2168
#define R300_VAP_INPUT_ROUTE_0_7 0x216C
#define R300_VAP_PROG_STREAM_CNTL_0 0x2150
# define R300_DATA_TYPE_0_SHIFT 0
# define R300_DATA_TYPE_FLOAT_1 0
# define R300_DATA_TYPE_FLOAT_2 1
# define R300_DATA_TYPE_FLOAT_3 2
# define R300_DATA_TYPE_FLOAT_4 3
# define R300_DATA_TYPE_BYTE 4
# define R300_DATA_TYPE_D3DCOLOR 5
# define R300_DATA_TYPE_SHORT_2 6
# define R300_DATA_TYPE_SHORT_4 7
# define R300_DATA_TYPE_VECTOR_3_TTT 8
# define R300_DATA_TYPE_VECTOR_3_EET 9
# define R300_SKIP_DWORDS_SHIFT 4
# define R300_DST_VEC_LOC_SHIFT 8
# define R300_LAST_VEC (1 << 13)
# define R300_SIGNED (1 << 14)
# define R300_NORMALIZE (1 << 15)
# define R300_DATA_TYPE_1_SHIFT 16
#define R300_VAP_PROG_STREAM_CNTL_1 0x2154
#define R300_VAP_PROG_STREAM_CNTL_2 0x2158
#define R300_VAP_PROG_STREAM_CNTL_3 0x215C
#define R300_VAP_PROG_STREAM_CNTL_4 0x2160
#define R300_VAP_PROG_STREAM_CNTL_5 0x2164
#define R300_VAP_PROG_STREAM_CNTL_6 0x2168
#define R300_VAP_PROG_STREAM_CNTL_7 0x216C
/* gap */
/* Notes:
@@ -239,9 +249,26 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* if vertex program uses only position, fglrx will set normal, too
* - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
*/
#define R300_VAP_INPUT_CNTL_0 0x2180
# define R300_INPUT_CNTL_0_COLOR 0x00000001
#define R300_VAP_INPUT_CNTL_1 0x2184
#define R300_VAP_VTX_STATE_CNTL 0x2180
# define R300_COLOR_0_ASSEMBLY_SHIFT 0
# define R300_SEL_COLOR 0
# define R300_SEL_USER_COLOR_0 1
# define R300_SEL_USER_COLOR_1 2
# define R300_COLOR_1_ASSEMBLY_SHIFT 2
# define R300_COLOR_2_ASSEMBLY_SHIFT 4
# define R300_COLOR_3_ASSEMBLY_SHIFT 6
# define R300_COLOR_4_ASSEMBLY_SHIFT 8
# define R300_COLOR_5_ASSEMBLY_SHIFT 10
# define R300_COLOR_6_ASSEMBLY_SHIFT 12
# define R300_COLOR_7_ASSEMBLY_SHIFT 14
# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16)
/*
* Each bit in this field applies to the corresponding vector in the VSM
* memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit
* is set, then the corresponding 4-Dword Vector is output into the Vertex Stream.
*/
#define R300_VAP_VSM_VTX_ASSM 0x2184
# define R300_INPUT_CNTL_POS 0x00000001
# define R300_INPUT_CNTL_NORMAL 0x00000002
# define R300_INPUT_CNTL_COLOR 0x00000004
@@ -269,26 +296,40 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* mode, the swizzling pattern is e.g. used to set zw components in texture
* coordinates with only tweo components.
*/
#define R300_VAP_INPUT_ROUTE_1_0 0x21E0
#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
# define R300_SWIZZLE0_SHIFT 0
# define R300_SWIZZLE_SELECT_X_SHIFT 0
# define R300_SWIZZLE_SELECT_Y_SHIFT 3
# define R300_SWIZZLE_SELECT_Z_SHIFT 6
# define R300_SWIZZLE_SELECT_W_SHIFT 9
# define R300_SWIZZLE_SELECT_X 0
# define R300_SWIZZLE_SELECT_Y 1
# define R300_SWIZZLE_SELECT_Z 2
# define R300_SWIZZLE_SELECT_W 3
# define R300_SWIZZLE_SELECT_FP_ZERO 4
# define R300_SWIZZLE_SELECT_FP_ONE 5
/* alternate forms for r300_emit.c */
# define R300_INPUT_ROUTE_SELECT_X 0
# define R300_INPUT_ROUTE_SELECT_Y 1
# define R300_INPUT_ROUTE_SELECT_Z 2
# define R300_INPUT_ROUTE_SELECT_W 3
# define R300_INPUT_ROUTE_SELECT_ZERO 4
# define R300_INPUT_ROUTE_SELECT_ONE 5
# define R300_INPUT_ROUTE_SELECT_MASK 7
# define R300_INPUT_ROUTE_X_SHIFT 0
# define R300_INPUT_ROUTE_Y_SHIFT 3
# define R300_INPUT_ROUTE_Z_SHIFT 6
# define R300_INPUT_ROUTE_W_SHIFT 9
# define R300_INPUT_ROUTE_ENABLE (15 << 12)
#define R300_VAP_INPUT_ROUTE_1_1 0x21E4
#define R300_VAP_INPUT_ROUTE_1_2 0x21E8
#define R300_VAP_INPUT_ROUTE_1_3 0x21EC
#define R300_VAP_INPUT_ROUTE_1_4 0x21F0
#define R300_VAP_INPUT_ROUTE_1_5 0x21F4
#define R300_VAP_INPUT_ROUTE_1_6 0x21F8
#define R300_VAP_INPUT_ROUTE_1_7 0x21FC
# define R300_WRITE_ENA_SHIFT 12
# define R300_WRITE_ENA_X 1
# define R300_WRITE_ENA_Y 2
# define R300_WRITE_ENA_Z 4
# define R300_WRITE_ENA_W 8
# define R300_SWIZZLE1_SHIFT 16
#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8
#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec
#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0
#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4
#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8
#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc
/* END: Vertex data assembly */
@@ -320,25 +361,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* Multiple vertex programs and parameter sets can be loaded at once,
* which could explain the size discrepancy.
*/
#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
# define R300_PVS_UPLOAD_PROGRAM 0x00000000
/* gap */
# define R300_PVS_UPLOAD_PARAMETERS 0x00000200
/* gap */
# define R300_PVS_UPLOAD_CLIP_PLANE0 0x00000400
# define R300_PVS_UPLOAD_CLIP_PLANE1 0x00000401
# define R300_PVS_UPLOAD_CLIP_PLANE2 0x00000402
# define R300_PVS_UPLOAD_CLIP_PLANE3 0x00000403
# define R300_PVS_UPLOAD_CLIP_PLANE4 0x00000404
# define R300_PVS_UPLOAD_CLIP_PLANE5 0x00000405
# define R300_PVS_UPLOAD_POINTSIZE 0x00000406
# define R500_PVS_UPLOAD_CLIP_PLANE0 0x00000600
# define R500_PVS_UPLOAD_CLIP_PLANE1 0x00000601
# define R500_PVS_UPLOAD_CLIP_PLANE2 0x00000602
# define R500_PVS_UPLOAD_CLIP_PLANE3 0x00000603
# define R500_PVS_UPLOAD_CLIP_PLANE4 0x00000604
# define R500_PVS_UPLOAD_CLIP_PLANE5 0x00000605
#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
# define R300_PVS_CODE_START 0
# define R300_MAX_PVS_CODE_LINES 256
# define R500_MAX_PVS_CODE_LINES 1024
# define R300_PVS_CONST_START 512
# define R500_PVS_CONST_START 1024
# define R300_MAX_PVS_CONST_VECS 256
# define R500_MAX_PVS_CONST_VECS 1024
# define R300_PVS_UCP_START 1024
# define R500_PVS_UCP_START 1536
# define R300_POINT_VPORT_SCALE_OFFSET 1030
# define R500_POINT_VPORT_SCALE_OFFSET 1542
# define R300_POINT_GEN_TEX_OFFSET 1031
# define R500_POINT_GEN_TEX_OFFSET 1543
/*
* These are obsolete defines form r300_context.h, but they might give some
@@ -373,9 +409,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view
*/
#define R300_VAP_CLIP_CNTL 0x221C
# define R300_221C_NORMAL 0x00000000
# define R300_221C_CLEAR 0x0001C000
#define R300_VAP_UCP_ENABLE_0 (1 << 0)
# define R300_VAP_UCP_ENABLE_0 (1 << 0)
# define R300_VAP_UCP_ENABLE_1 (1 << 1)
# define R300_VAP_UCP_ENABLE_2 (1 << 2)
# define R300_VAP_UCP_ENABLE_3 (1 << 3)
# define R300_VAP_UCP_ENABLE_4 (1 << 4)
# define R300_VAP_UCP_ENABLE_5 (1 << 5)
# define R300_PS_UCP_MODE_DIST_COP (0 << 14)
# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14)
# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14)
# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14)
# define R300_CLIP_DISABLE (1 << 16)
# define R300_UCP_CULL_ONLY_ENABLE (1 << 17)
# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18)
# define R500_COLOR2_IS_TEXTURE (1 << 20)
# define R500_COLOR3_IS_TEXTURE (1 << 21)
/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
* plane is per-pixel and the second plane is per-vertex.
src/mesa/drivers/dri/r300/r300_state.c
+46 -10
View File
@@ -1802,7 +1802,7 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
prog->program.length = program_end;
r300SetupVertexProgramFragment(rmesa, R300_PVS_UPLOAD_PROGRAM,
r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START,
&(prog->program));
inst_count = (prog->program.length / 4) - 1;
@@ -1837,7 +1837,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
bump_vpu_count(rmesa->hw.vpp.cmd, param_count);
param_count /= 4;
r300SetupVertexProgramFragment(rmesa, R300_PVS_UPLOAD_PROGRAM, &(prog->program));
r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, &(prog->program));
inst_count = (prog->program.length / 4) - 1;
R300_STATECHANGE(rmesa, pvs);
@@ -1981,10 +1981,34 @@ static void r300ResetHwState(r300ContextPtr r300)
r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
if (!has_tcl)
r300->hw.vap_cntl.cmd[1] = 0x0014045a;
/* setup the VAP */
/* for tcl, PVS_NUM_SLOTS, PVS_NUM_CNTLRS, VF_MAX_VTX_NUM need to be adjusted
* dynamically. PVS_NUM_FPUS is fixed based on asic
*/
if (has_tcl) {
r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(12 << R300_VF_MAX_VTX_NUM_SHIFT));
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r300->hw.vap_cntl.cmd[1] |= R500_TCL_STATE_OPTIMIZATION;
} else
r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(5 << R300_VF_MAX_VTX_NUM_SHIFT));
if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
r300->hw.vap_cntl.cmd[1] |= (2 << R300_PVS_NUM_FPUS_SHIFT);
else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560))
r300->hw.vap_cntl.cmd[1] |= (5 << R300_PVS_NUM_FPUS_SHIFT);
else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)
r300->hw.vap_cntl.cmd[1] |= (6 << R300_PVS_NUM_FPUS_SHIFT);
else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
r300->hw.vap_cntl.cmd[1] |= (8 << R300_PVS_NUM_FPUS_SHIFT);
else
r300->hw.vap_cntl.cmd[1] = 0x0030045A; //0x0030065a /* Dangerous */
r300->hw.vap_cntl.cmd[1] |= (4 << R300_PVS_NUM_FPUS_SHIFT);
r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
| R300_VPORT_X_OFFSET_ENA
@@ -2011,7 +2035,7 @@ static void r300ResetHwState(r300ContextPtr r300)
/* XXX: Other families? */
if (has_tcl) {
r300->hw.vap_clip_cntl.cmd[1] = R300_221C_NORMAL;
r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP;
r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
@@ -2035,19 +2059,30 @@ static void r300ResetHwState(r300ContextPtr r300)
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
/* XXX: Other families? */
/* num pipes needs to be read back from the GB_PIPE_SELECT register
* on r4xx/r5xx/rs4xx/rs6xx
* should move this to the drm
*/
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16;
R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
switch (r300->radeon.radeonScreen->chip_family) {
case CHIP_FAMILY_R300:
case CHIP_FAMILY_R350:
case CHIP_FAMILY_RV410:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
R300_GB_TILE_PIPE_COUNT_R300;
break;
case CHIP_FAMILY_R420:
case CHIP_FAMILY_RV350:
case CHIP_FAMILY_RV515:
case CHIP_FAMILY_RV530:
case CHIP_FAMILY_RV410:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
R300_GB_TILE_PIPE_COUNT_RV300;
break;
case CHIP_FAMILY_R420:
case CHIP_FAMILY_R520:
case CHIP_FAMILY_R580:
case CHIP_FAMILY_RV560:
case CHIP_FAMILY_RV570:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
R300_GB_TILE_PIPE_COUNT_R420;
break;
@@ -2342,6 +2377,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa)
bump_r500fp_count(rmesa->hw.r500fp.cmd, fp->cs->nrslots * 6);
R300_STATECHANGE(rmesa, r500fp_const);
for (i = 0; i < fp->const_nr; i++) {
rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(fp->constant[i][0]);
src/mesa/drivers/dri/r300/r300_swtcl.c
+16 -11
View File
@@ -85,21 +85,26 @@ static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
GLuint i, dw;
/* type, inputs, stop bit, size */
for (i = 0; i + 1 < nr; i += 2) {
dw = (inputs[tab[i]] << 8) | 0x3;
dw |= ((inputs[tab[i + 1]] << 8) | 0x3) << 16;
if (i + 2 == nr) {
dw |= (R300_VAP_INPUT_ROUTE_END << 16);
for (i = 0; i < nr; i += 2) {
/* make sure input is valid, would lockup the gpu */
assert(inputs[tab[i]] != -1);
dw = (R300_SIGNED |
(inputs[tab[i]] << R300_DST_VEC_LOC_SHIFT) |
(attribptr[tab[i]]->size - 1)) << R300_DATA_TYPE_0_SHIFT;
if (i + 1 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
} else {
assert(inputs[tab[i + 1]] != -1);
dw |= (R300_SIGNED |
(inputs[tab[i + 1]] << R300_DST_VEC_LOC_SHIFT) |
(attribptr[tab[i + 1]]->size - 1)) << R300_DATA_TYPE_1_SHIFT;
if (i + 2 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
}
}
dst[i >> 1] = dw;
}
if (nr & 1) {
dw = (inputs[tab[nr - 1]] << 8) | 0x3;
dw |= R300_VAP_INPUT_ROUTE_END;
dst[nr >> 1] = dw;
}
return (nr + 1) >> 1;
}
src/mesa/drivers/dri/radeon/radeon_chipset.h
+105 -2
View File
@@ -147,13 +147,111 @@
#define PCI_CHIP_RV410_5E4D 0x5E4D
#define PCI_CHIP_RV410_5E4F 0x5E4F
#define PCI_CHIP_RV530_71C4 0x71C4
#define PCI_CHIP_RV530_71D5 0x71D5
#define PCI_CHIP_R520_7100 0x7100
#define PCI_CHIP_R520_7101 0x7101
#define PCI_CHIP_R520_7102 0x7102
#define PCI_CHIP_R520_7103 0x7103
#define PCI_CHIP_R520_7104 0x7104
#define PCI_CHIP_R520_7105 0x7105
#define PCI_CHIP_R520_7106 0x7106
#define PCI_CHIP_R520_7108 0x7108
#define PCI_CHIP_R520_7109 0x7109
#define PCI_CHIP_R520_710A 0x710A
#define PCI_CHIP_R520_710B 0x710B
#define PCI_CHIP_R520_710C 0x710C
#define PCI_CHIP_R520_710E 0x710E
#define PCI_CHIP_R520_710F 0x710F
#define PCI_CHIP_RV515_7140 0x7140
#define PCI_CHIP_RV515_7141 0x7141
#define PCI_CHIP_RV515_7142 0x7142
#define PCI_CHIP_RV515_7143 0x7143
#define PCI_CHIP_RV515_7144 0x7144
#define PCI_CHIP_RV515_7145 0x7145
#define PCI_CHIP_RV515_7146 0x7146
#define PCI_CHIP_RV515_7147 0x7147
#define PCI_CHIP_RV515_7149 0x7149
#define PCI_CHIP_RV515_714A 0x714A
#define PCI_CHIP_RV515_714B 0x714B
#define PCI_CHIP_RV515_714C 0x714C
#define PCI_CHIP_RV515_714D 0x714D
#define PCI_CHIP_RV515_714E 0x714E
#define PCI_CHIP_RV515_714F 0x714F
#define PCI_CHIP_RV515_7151 0x7151
#define PCI_CHIP_RV515_7152 0x7152
#define PCI_CHIP_RV515_7153 0x7153
#define PCI_CHIP_RV515_715E 0x715E
#define PCI_CHIP_RV515_715F 0x715F
#define PCI_CHIP_RV515_7180 0x7180
#define PCI_CHIP_RV515_7181 0x7181
#define PCI_CHIP_RV515_7183 0x7183
#define PCI_CHIP_RV515_7186 0x7186
#define PCI_CHIP_RV515_7187 0x7187
#define PCI_CHIP_RV515_7188 0x7188
#define PCI_CHIP_RV515_718A 0x718A
#define PCI_CHIP_RV515_718B 0x718B
#define PCI_CHIP_RV515_718C 0x718C
#define PCI_CHIP_RV515_718D 0x718D
#define PCI_CHIP_RV515_718F 0x718F
#define PCI_CHIP_RV515_7193 0x7193
#define PCI_CHIP_RV515_7196 0x7196
#define PCI_CHIP_RV515_719B 0x719B
#define PCI_CHIP_RV515_719F 0x719F
#define PCI_CHIP_RV530_71C0 0x71C0
#define PCI_CHIP_RV530_71C1 0x71C1
#define PCI_CHIP_RV530_71C2 0x71C2
#define PCI_CHIP_RV530_71C3 0x71C3
#define PCI_CHIP_RV530_71C4 0x71C4
#define PCI_CHIP_RV530_71C5 0x71C5
#define PCI_CHIP_RV530_71C6 0x71C6
#define PCI_CHIP_RV530_71C7 0x71C7
#define PCI_CHIP_RV530_71CD 0x71CD
#define PCI_CHIP_RV530_71CE 0x71CE
#define PCI_CHIP_RV530_71D2 0x71D2
#define PCI_CHIP_RV530_71D4 0x71D4
#define PCI_CHIP_RV530_71D5 0x71D5
#define PCI_CHIP_RV530_71D6 0x71D6
#define PCI_CHIP_RV530_71DA 0x71DA
#define PCI_CHIP_RV530_71DE 0x71DE
#define PCI_CHIP_RV515_7200 0x7200
#define PCI_CHIP_RV515_7210 0x7210
#define PCI_CHIP_RV515_7211 0x7211
#define PCI_CHIP_R580_7240 0x7240
#define PCI_CHIP_R580_7243 0x7243
#define PCI_CHIP_R580_7244 0x7244
#define PCI_CHIP_R580_7245 0x7245
#define PCI_CHIP_R580_7246 0x7246
#define PCI_CHIP_R580_7247 0x7247
#define PCI_CHIP_R580_7248 0x7248
#define PCI_CHIP_R580_7249 0x7249
#define PCI_CHIP_R580_724A 0x724A
#define PCI_CHIP_R580_724B 0x724B
#define PCI_CHIP_R580_724C 0x724C
#define PCI_CHIP_R580_724D 0x724D
#define PCI_CHIP_R580_724E 0x724E
#define PCI_CHIP_R580_724F 0x724F
#define PCI_CHIP_RV570_7280 0x7280
#define PCI_CHIP_RV560_7281 0x7281
#define PCI_CHIP_RV560_7283 0x7283
#define PCI_CHIP_R580_7284 0x7284
#define PCI_CHIP_RV560_7287 0x7287
#define PCI_CHIP_RV570_7288 0x7288
#define PCI_CHIP_RV570_7289 0x7289
#define PCI_CHIP_RV570_728B 0x728B
#define PCI_CHIP_RV570_728C 0x728C
#define PCI_CHIP_RV560_7290 0x7290
#define PCI_CHIP_RV560_7291 0x7291
#define PCI_CHIP_RV560_7293 0x7293
#define PCI_CHIP_RV560_7297 0x7297
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
#define PCI_CHIP_RS690_791E 0x791E
#define PCI_CHIP_RS690_791F 0x791F
#define PCI_CHIP_RS740_796C 0x796C
#define PCI_CHIP_RS740_796D 0x796D
#define PCI_CHIP_RS740_796E 0x796E
#define PCI_CHIP_RS740_796F 0x796F
enum {
CHIP_FAMILY_R100,
@@ -173,8 +271,13 @@ enum {
CHIP_FAMILY_RV410,
CHIP_FAMILY_RS400,
CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
CHIP_FAMILY_RV515,
CHIP_FAMILY_R520,
CHIP_FAMILY_RV530,
CHIP_FAMILY_R580,
CHIP_FAMILY_RV560,
CHIP_FAMILY_RV570,
CHIP_FAMILY_LAST
};
src/mesa/drivers/dri/radeon/radeon_screen.c
+124 -4
View File
@@ -649,7 +649,9 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
/* RV410 SE chips have half the pipes of regular RV410 */
/* RV410 SE chips have half the pipes of regular RV410
* Need to get num pipes form the GB_PIPE_SELECT register
*/
case PCI_CHIP_RV410_5E4C:
case PCI_CHIP_RV410_5E4F:
screen->chip_family = CHIP_FAMILY_RV380;
@@ -682,18 +684,136 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
break;
case PCI_CHIP_RS690_791E:
case PCI_CHIP_RS690_791F:
screen->chip_family = CHIP_FAMILY_RS690;
fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n");
break;
case PCI_CHIP_RS740_796C:
case PCI_CHIP_RS740_796D:
case PCI_CHIP_RS740_796E:
case PCI_CHIP_RS740_796F:
screen->chip_family = CHIP_FAMILY_RS740;
fprintf(stderr, "Warning, RS740 detected, 3D support is incomplete.\n");
break;
case PCI_CHIP_RV530_71C4:
case PCI_CHIP_R520_7100:
case PCI_CHIP_R520_7101:
case PCI_CHIP_R520_7102:
case PCI_CHIP_R520_7103:
case PCI_CHIP_R520_7104:
case PCI_CHIP_R520_7105:
case PCI_CHIP_R520_7106:
case PCI_CHIP_R520_7108:
case PCI_CHIP_R520_7109:
case PCI_CHIP_R520_710A:
case PCI_CHIP_R520_710B:
case PCI_CHIP_R520_710C:
case PCI_CHIP_R520_710E:
case PCI_CHIP_R520_710F:
screen->chip_family = CHIP_FAMILY_R520;
screen->chip_flags = RADEON_CHIPSET_TCL;
fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n");
break;
case PCI_CHIP_RV515_7140:
case PCI_CHIP_RV515_7141:
case PCI_CHIP_RV515_7142:
case PCI_CHIP_RV515_7143:
case PCI_CHIP_RV515_7144:
case PCI_CHIP_RV515_7145:
case PCI_CHIP_RV515_7146:
case PCI_CHIP_RV515_7147:
case PCI_CHIP_RV515_7149:
case PCI_CHIP_RV515_714A:
case PCI_CHIP_RV515_714B:
case PCI_CHIP_RV515_714C:
case PCI_CHIP_RV515_714D:
case PCI_CHIP_RV515_714E:
case PCI_CHIP_RV515_714F:
case PCI_CHIP_RV515_7151:
case PCI_CHIP_RV515_7152:
case PCI_CHIP_RV515_7153:
case PCI_CHIP_RV515_715E:
case PCI_CHIP_RV515_715F:
case PCI_CHIP_RV515_7180:
case PCI_CHIP_RV515_7181:
case PCI_CHIP_RV515_7183:
case PCI_CHIP_RV515_7186:
case PCI_CHIP_RV515_7187:
case PCI_CHIP_RV515_7188:
case PCI_CHIP_RV515_718A:
case PCI_CHIP_RV515_718B:
case PCI_CHIP_RV515_718C:
case PCI_CHIP_RV515_718D:
case PCI_CHIP_RV515_718F:
case PCI_CHIP_RV515_7193:
case PCI_CHIP_RV515_7196:
case PCI_CHIP_RV515_719B:
case PCI_CHIP_RV515_719F:
case PCI_CHIP_RV515_7200:
case PCI_CHIP_RV515_7210:
case PCI_CHIP_RV515_7211:
screen->chip_family = CHIP_FAMILY_RV515;
screen->chip_flags = RADEON_CHIPSET_TCL;
fprintf(stderr, "Warning, RV515 detected, 3D HAHAHAHAHA!!.\n");
break;
case PCI_CHIP_RV530_71C0:
case PCI_CHIP_RV530_71C1:
case PCI_CHIP_RV530_71C2:
case PCI_CHIP_RV530_71C3:
case PCI_CHIP_RV530_71C4:
case PCI_CHIP_RV530_71C5:
case PCI_CHIP_RV530_71C6:
case PCI_CHIP_RV530_71C7:
case PCI_CHIP_RV530_71CD:
case PCI_CHIP_RV530_71CE:
case PCI_CHIP_RV530_71D2:
case PCI_CHIP_RV530_71D4:
case PCI_CHIP_RV530_71D5:
screen->chip_family = CHIP_FAMILY_R520;
fprintf(stderr, "Warning, RV530 detected, all your base belong to us\n");
case PCI_CHIP_RV530_71D6:
case PCI_CHIP_RV530_71DA:
case PCI_CHIP_RV530_71DE:
screen->chip_family = CHIP_FAMILY_RV530;
screen->chip_flags = RADEON_CHIPSET_TCL;
fprintf(stderr, "Warning, RV530 detected, 3D HAHAHAHAHA!!.\n");
break;
case PCI_CHIP_R580_7240:
case PCI_CHIP_R580_7243:
case PCI_CHIP_R580_7244:
case PCI_CHIP_R580_7245:
case PCI_CHIP_R580_7246:
case PCI_CHIP_R580_7247:
case PCI_CHIP_R580_7248:
case PCI_CHIP_R580_7249:
case PCI_CHIP_R580_724A:
case PCI_CHIP_R580_724B:
case PCI_CHIP_R580_724C:
case PCI_CHIP_R580_724D:
case PCI_CHIP_R580_724E:
case PCI_CHIP_R580_724F:
case PCI_CHIP_R580_7284:
screen->chip_family = CHIP_FAMILY_R580;
screen->chip_flags = RADEON_CHIPSET_TCL;
fprintf(stderr, "Warning, R580 detected, 3D HAHAHAHAHA!!.\n");
break;
case PCI_CHIP_RV570_7280:
case PCI_CHIP_RV560_7281:
case PCI_CHIP_RV560_7283:
case PCI_CHIP_RV560_7287:
case PCI_CHIP_RV570_7288:
case PCI_CHIP_RV570_7289:
case PCI_CHIP_RV570_728B:
case PCI_CHIP_RV570_728C:
case PCI_CHIP_RV560_7290:
case PCI_CHIP_RV560_7291:
case PCI_CHIP_RV560_7293:
case PCI_CHIP_RV560_7297:
screen->chip_family = CHIP_FAMILY_RV560;
screen->chip_flags = RADEON_CHIPSET_TCL;
fprintf(stderr, "Warning, RV560 detected, 3D HAHAHAHAHA!!.\n");
break;
default: