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i965g: more compiling wip

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This commit is contained in:
Keith Whitwell
2009-10-25 01:20:56 +01:00
parent 4dd2f6640b
commit 562ca4eae2
16 changed files with 244 additions and 201 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/i965/brw_context.h
+11 -4
View File
@@ -184,6 +184,8 @@ struct brw_fragment_shader {
#define PIPE_NEW_CLIP 0x2
#define PIPE_NEW_INDEX_BUFFER 0x2
#define PIPE_NEW_INDEX_RANGE 0x2
#define PIPE_NEW_BLEND_COLOR 0x2
#define PIPE_NEW_POLYGON_STIPPLE 0x2
#define BRW_NEW_URB_FENCE 0x1
@@ -202,7 +204,9 @@ struct brw_fragment_shader {
#define BRW_NEW_VERTICES 0x8000
/**
* Used for any batch entry with a relocated pointer that will be used
* by any 3D rendering.
* by any 3D rendering. Need to re-emit these fresh in each
* batchbuffer as the referenced buffers may be relocated in the
* meantime.
*/
#define BRW_NEW_BATCH 0x10000
/** brw->depth_region updated */
@@ -271,7 +275,7 @@ struct brw_vs_prog_data {
GLuint curb_read_length;
GLuint urb_read_length;
GLuint total_grf;
GLuint outputs_written;
GLuint nr_outputs_written;
GLuint nr_params; /**< number of float params/constants */
GLuint inputs_read;
@@ -487,6 +491,9 @@ struct brw_context
struct pipe_buffer *vertex_constants;
struct pipe_buffer *fragment_constants;
struct brw_blend_constant_color bcc;
struct brw_polygon_stipple bps;
/**
* Index buffer for this draw_prims call.
*
@@ -726,11 +733,11 @@ void brw_init_shader_funcs( struct brw_context *brw );
/* brw_urb.c
*/
void brw_upload_urb_fence(struct brw_context *brw);
int brw_upload_urb_fence(struct brw_context *brw);
/* brw_curbe.c
*/
void brw_upload_cs_urb_state(struct brw_context *brw);
int brw_upload_cs_urb_state(struct brw_context *brw);
/* brw_disasm.c */
int brw_disasm (FILE *file, struct brw_instruction *inst);
src/gallium/drivers/i965/brw_curbe.c
+2 -1
View File
@@ -126,7 +126,7 @@ const struct brw_tracked_state brw_curbe_offsets = {
* fixed-function hardware in a double-buffering scheme to avoid a
* pipeline stall each time the contents of the curbe is changed.
*/
void brw_upload_cs_urb_state(struct brw_context *brw)
int brw_upload_cs_urb_state(struct brw_context *brw)
{
struct brw_cs_urb_state cs_urb;
memset(&cs_urb, 0, sizeof(cs_urb));
@@ -144,6 +144,7 @@ void brw_upload_cs_urb_state(struct brw_context *brw)
assert(brw->urb.nr_cs_entries);
BRW_CACHED_BATCH_STRUCT(brw, &cs_urb);
return 0;
}
static GLfloat fixed_plane[6][4] = {
src/gallium/drivers/i965/brw_gs.c
+25 -23
View File
@@ -54,7 +54,7 @@ static void compile_gs_prog( struct brw_context *brw,
/* Need to locate the two positions present in vertex + header.
* These are currently hardcoded:
*/
c.nr_attrs = util_count_bits(c.key.attrs);
c.nr_attrs = c.key.nr_attrs;
if (BRW_IS_IGDNG(brw))
c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
@@ -80,30 +80,30 @@ static void compile_gs_prog( struct brw_context *brw,
* already been weeded out by this stage:
*/
switch (key->primitive) {
case GL_QUADS:
case PIPE_PRIM_QUADS:
brw_gs_quads( &c );
break;
case GL_QUAD_STRIP:
case PIPE_PRIM_QUAD_STRIP:
brw_gs_quad_strip( &c );
break;
case GL_LINE_LOOP:
case PIPE_PRIM_LINE_LOOP:
brw_gs_lines( &c );
break;
case GL_LINES:
case PIPE_PRIM_LINES:
if (key->hint_gs_always)
brw_gs_lines( &c );
else {
return;
}
break;
case GL_TRIANGLES:
case PIPE_PRIM_TRIANGLES:
if (key->hint_gs_always)
brw_gs_tris( &c );
else {
return;
}
break;
case GL_POINTS:
case PIPE_PRIM_POINTS:
if (key->hint_gs_always)
brw_gs_points( &c );
else {
@@ -129,17 +129,17 @@ static void compile_gs_prog( struct brw_context *brw,
&brw->gs.prog_data );
}
static const GLenum gs_prim[GL_POLYGON+1] = {
GL_POINTS,
GL_LINES,
GL_LINE_LOOP,
GL_LINES,
GL_TRIANGLES,
GL_TRIANGLES,
GL_TRIANGLES,
GL_QUADS,
GL_QUAD_STRIP,
GL_TRIANGLES
static const unsigned gs_prim[PIPE_PRIM_MAX] = {
PIPE_PRIM_POINTS,
PIPE_PRIM_LINES,
PIPE_PRIM_LINE_LOOP,
PIPE_PRIM_LINES,
PIPE_PRIM_TRIANGLES,
PIPE_PRIM_TRIANGLES,
PIPE_PRIM_TRIANGLES,
PIPE_PRIM_QUADS,
PIPE_PRIM_QUAD_STRIP,
PIPE_PRIM_TRIANGLES
};
static void populate_key( struct brw_context *brw,
@@ -148,7 +148,7 @@ static void populate_key( struct brw_context *brw,
memset(key, 0, sizeof(*key));
/* CACHE_NEW_VS_PROG */
key->attrs = brw->vs.prog_data->outputs_written;
key->nr_attrs = brw->vs.prog_data->nr_outputs_written;
/* BRW_NEW_PRIMITIVE */
key->primitive = gs_prim[brw->primitive];
@@ -156,14 +156,14 @@ static void populate_key( struct brw_context *brw,
key->hint_gs_always = 0; /* debug code? */
key->need_gs_prog = (key->hint_gs_always ||
brw->primitive == GL_QUADS ||
brw->primitive == GL_QUAD_STRIP ||
brw->primitive == GL_LINE_LOOP);
brw->primitive == PIPE_PRIM_QUADS ||
brw->primitive == PIPE_PRIM_QUAD_STRIP ||
brw->primitive == PIPE_PRIM_LINE_LOOP);
}
/* Calculate interpolants for triangle and line rasterization.
*/
static void prepare_gs_prog(struct brw_context *brw)
static int prepare_gs_prog(struct brw_context *brw)
{
struct brw_gs_prog_key key;
/* Populate the key:
@@ -184,6 +184,8 @@ static void prepare_gs_prog(struct brw_context *brw)
if (brw->gs.prog_bo == NULL)
compile_gs_prog( brw, &key );
}
return 0;
}
src/gallium/drivers/i965/brw_gs.h
+2 -2
View File
@@ -40,11 +40,11 @@
#define MAX_GS_VERTS (4)
struct brw_gs_prog_key {
GLuint attrs:32;
GLuint nr_attrs:8;
GLuint primitive:4;
GLuint hint_gs_always:1;
GLuint need_gs_prog:1;
GLuint pad:26;
GLuint pad:18;
};
struct brw_gs_compile {
src/gallium/drivers/i965/brw_gs_state.c
+12 -9
View File
@@ -29,11 +29,12 @@
* Keith Whitwell <keith@tungstengraphics.com>
*/
#include "util/u_math.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_debug.h"
struct brw_gs_unit_key {
unsigned int total_grf;
@@ -76,7 +77,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
memset(&gs, 0, sizeof(gs));
gs.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
gs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
if (key->prog_active) /* reloc */
gs.thread0.kernel_start_pointer = brw->gs.prog_bo->offset >> 6;
@@ -100,7 +101,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (BRW_IS_IGDNG(brw))
gs.thread4.rendering_enable = 1;
if (INTEL_DEBUG & DEBUG_STATS)
if (BRW_DEBUG & DEBUG_STATS)
gs.thread4.stats_enable = 1;
bo = brw_upload_cache(&brw->cache, BRW_GS_UNIT,
@@ -111,17 +112,17 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
gs.thread0.grf_reg_count << 1,
offsetof(struct brw_gs_unit_state, thread0),
brw->gs.prog_bo);
brw->sws->bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
gs.thread0.grf_reg_count << 1,
offsetof(struct brw_gs_unit_state, thread0),
brw->gs.prog_bo);
}
return bo;
}
static void prepare_gs_unit(struct brw_context *brw)
static int prepare_gs_unit(struct brw_context *brw)
{
struct brw_gs_unit_key key;
@@ -135,6 +136,8 @@ static void prepare_gs_unit(struct brw_context *brw)
if (brw->gs.state_bo == NULL) {
brw->gs.state_bo = gs_unit_create_from_key(brw, &key);
}
return 0;
}
const struct brw_tracked_state brw_gs_unit = {
src/gallium/drivers/i965/brw_misc_state.c
+103 -119
View File
@@ -31,10 +31,12 @@
#include "brw_debug.h"
#include "brw_batchbuffer.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_screen.h"
@@ -44,25 +46,16 @@
* Blend color
*/
static void upload_blend_constant_color(struct brw_context *brw)
static int upload_blend_constant_color(struct brw_context *brw)
{
struct brw_blend_constant_color bcc;
memset(&bcc, 0, sizeof(bcc));
bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
bcc.header.length = sizeof(bcc)/4-2;
bcc.blend_constant_color[0] = ctx->Color.BlendColor[0];
bcc.blend_constant_color[1] = ctx->Color.BlendColor[1];
bcc.blend_constant_color[2] = ctx->Color.BlendColor[2];
bcc.blend_constant_color[3] = ctx->Color.BlendColor[3];
BRW_CACHED_BATCH_STRUCT(brw, &bcc);
BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bcc);
return 0;
}
const struct brw_tracked_state brw_blend_constant_color = {
.dirty = {
.mesa = _NEW_COLOR,
.mesa = PIPE_NEW_BLEND_COLOR,
.brw = 0,
.cache = 0
},
@@ -70,30 +63,32 @@ const struct brw_tracked_state brw_blend_constant_color = {
};
/* Constant single cliprect for framebuffer object or DRI2 drawing */
static void upload_drawing_rect(struct brw_context *brw)
static int upload_drawing_rect(struct brw_context *brw)
{
BEGIN_BATCH(4, NO_LOOP_CLIPRECTS);
OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
OUT_BATCH(0);
OUT_BATCH(((brw->fb.width - 1) & 0xffff) |
((brw->fb.height - 1) << 16));
OUT_BATCH(((brw->curr.fb.width - 1) & 0xffff) |
((brw->curr.fb.height - 1) << 16));
OUT_BATCH(0);
ADVANCE_BATCH();
return 0;
}
const struct brw_tracked_state brw_drawing_rect = {
.dirty = {
.mesa = _NEW_BUFFERS,
.mesa = PIPE_NEW_FRAMEBUFFER,
.brw = 0,
.cache = 0
},
.emit = upload_drawing_rect
};
static void prepare_binding_table_pointers(struct brw_context *brw)
static int prepare_binding_table_pointers(struct brw_context *brw)
{
brw_add_validated_bo(brw, brw->vs.bind_bo);
brw_add_validated_bo(brw, brw->wm.bind_bo);
return 0;
}
/**
@@ -103,7 +98,7 @@ static void prepare_binding_table_pointers(struct brw_context *brw)
* The binding table pointers are relative to the surface state base address,
* which is 0.
*/
static void upload_binding_table_pointers(struct brw_context *brw)
static int upload_binding_table_pointers(struct brw_context *brw)
{
BEGIN_BATCH(6, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
@@ -116,6 +111,7 @@ static void upload_binding_table_pointers(struct brw_context *brw)
OUT_BATCH(0); /* sf */
OUT_RELOC(brw->wm.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* wm/ps */
ADVANCE_BATCH();
return 0;
}
const struct brw_tracked_state brw_binding_table_pointers = {
@@ -135,7 +131,7 @@ const struct brw_tracked_state brw_binding_table_pointers = {
* The state pointers in this packet are all relative to the general state
* base address set by CMD_STATE_BASE_ADDRESS, which is 0.
*/
static void upload_pipelined_state_pointers(struct brw_context *brw )
static int upload_pipelined_state_pointers(struct brw_context *brw )
{
BEGIN_BATCH(7, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
@@ -151,10 +147,11 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
return 0;
}
static void prepare_psp_urb_cbs(struct brw_context *brw)
static int prepare_psp_urb_cbs(struct brw_context *brw)
{
brw_add_validated_bo(brw, brw->vs.state_bo);
brw_add_validated_bo(brw, brw->gs.state_bo);
@@ -162,13 +159,26 @@ static void prepare_psp_urb_cbs(struct brw_context *brw)
brw_add_validated_bo(brw, brw->sf.state_bo);
brw_add_validated_bo(brw, brw->wm.state_bo);
brw_add_validated_bo(brw, brw->cc.state_bo);
return 0;
}
static void upload_psp_urb_cbs(struct brw_context *brw )
static int upload_psp_urb_cbs(struct brw_context *brw )
{
upload_pipelined_state_pointers(brw);
brw_upload_urb_fence(brw);
brw_upload_cs_urb_state(brw);
int ret;
ret = upload_pipelined_state_pointers(brw);
if (ret)
return ret;
ret = brw_upload_urb_fence(brw);
if (ret)
return ret;
ret = brw_upload_cs_urb_state(brw);
if (ret)
return ret;
return 0;
}
const struct brw_tracked_state brw_psp_urb_cbs = {
@@ -187,20 +197,22 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
.emit = upload_psp_urb_cbs,
};
static void prepare_depthbuffer(struct brw_context *brw)
static int prepare_depthbuffer(struct brw_context *brw)
{
struct intel_region *region = brw->state.depth_region;
struct pipe_surface *zsbuf = brw->curr.fb.zsbuf;
if (region != NULL)
brw_add_validated_bo(brw, region->buffer);
if (zsbuf)
brw_add_validated_bo(brw, brw_surface_bo(zsbuf));
return 0;
}
static void emit_depthbuffer(struct brw_context *brw)
static int emit_depthbuffer(struct brw_context *brw)
{
struct intel_region *region = brw->state.depth_region;
struct pipe_surface *surface = brw->curr.fb.zsbuf;
unsigned int len = (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? 6 : 5;
if (region == NULL) {
if (surface == NULL) {
BEGIN_BATCH(len, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
@@ -214,38 +226,45 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
} else {
struct brw_winsys_buffer *bo;
unsigned int format;
unsigned int pitch;
unsigned int cpp;
switch (region->cpp) {
case 2:
switch (surface->format) {
case PIPE_FORMAT_Z16_UNORM:
format = BRW_DEPTHFORMAT_D16_UNORM;
cpp = 2;
break;
case 4:
if (intel->depth_buffer_is_float)
format = BRW_DEPTHFORMAT_D32_FLOAT;
else
format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
case PIPE_FORMAT_Z24S8_UNORM:
format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
cpp = 4;
break;
case PIPE_FORMAT_Z32_FLOAT:
format = BRW_DEPTHFORMAT_D32_FLOAT;
cpp = 4;
break;
default:
assert(0);
return;
return PIPE_ERROR_BAD_INPUT;
}
assert(region->tiling != I915_TILING_X);
bo = brw_surface_bo(surface);
pitch = brw_surface_pitch(surface);
BEGIN_BATCH(len, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH(((region->pitch * region->cpp) - 1) |
OUT_BATCH(((pitch * cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
((region->tiling != I915_TILING_NONE) << 27) |
((surface->layout != PIPE_SURFACE_LAYOUT_LINEAR) << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
OUT_RELOC(bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
surface->offset);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
((region->height - 1) << 19));
((pitch - 1) << 6) |
((surface->height - 1) << 19));
OUT_BATCH(0);
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
@@ -253,6 +272,8 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
}
return 0;
}
const struct brw_tracked_state brw_depthbuffer = {
@@ -271,37 +292,15 @@ const struct brw_tracked_state brw_depthbuffer = {
* Polygon stipple packet
*/
static void upload_polygon_stipple(struct brw_context *brw)
static int upload_polygon_stipple(struct brw_context *brw)
{
struct brw_polygon_stipple bps;
GLuint i;
memset(&bps, 0, sizeof(bps));
bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
bps.header.length = sizeof(bps)/4-2;
/* Polygon stipple is provided in OpenGL order, i.e. bottom
* row first. If we're rendering to a window (i.e. the
* default frame buffer object, 0), then we need to invert
* it to match our pixel layout. But if we're rendering
* to a FBO (i.e. any named frame buffer object), we *don't*
* need to invert - we already match the layout.
*/
if (ctx->DrawBuffer->Name == 0) {
for (i = 0; i < 32; i++)
bps.stipple[i] = ctx->PolygonStipple[31 - i]; /* invert */
}
else {
for (i = 0; i < 32; i++)
bps.stipple[i] = ctx->PolygonStipple[i]; /* don't invert */
}
BRW_CACHED_BATCH_STRUCT(brw, &bps);
BRW_CACHED_BATCH_STRUCT(brw, &brw->curr.bps);
return 0;
}
const struct brw_tracked_state brw_polygon_stipple = {
.dirty = {
.mesa = _NEW_POLYGONSTIPPLE,
.mesa = PIPE_NEW_POLYGON_STIPPLE,
.brw = 0,
.cache = 0
},
@@ -313,37 +312,26 @@ const struct brw_tracked_state brw_polygon_stipple = {
* Polygon stipple offset packet
*/
static void upload_polygon_stipple_offset(struct brw_context *brw)
static int upload_polygon_stipple_offset(struct brw_context *brw)
{
struct brw_polygon_stipple_offset bpso;
/* This is invarient state in gallium:
*/
memset(&bpso, 0, sizeof(bpso));
bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
bpso.header.length = sizeof(bpso)/4-2;
/* Never need to offset stipple coordinates.
*
* XXX: is it ever necessary to invert Y values?
*/
if (0) {
int x = 0, y = 0, h = 0;
bpso.bits0.x_offset = (32 - (x & 31)) & 31;
bpso.bits0.y_offset = (32 - ((y + h) & 31)) & 31;
}
else {
bpso.bits0.y_offset = 0;
bpso.bits0.x_offset = 0;
}
bpso.bits0.y_offset = 0;
bpso.bits0.x_offset = 0;
BRW_CACHED_BATCH_STRUCT(brw, &bpso);
return 0;
}
#define _NEW_WINDOW_POS 0x40000000
const struct brw_tracked_state brw_polygon_stipple_offset = {
.dirty = {
.mesa = _NEW_WINDOW_POS,
.brw = 0,
.mesa = 0,
.brw = BRW_NEW_CONTEXT,
.cache = 0
},
.emit = upload_polygon_stipple_offset
@@ -352,12 +340,12 @@ const struct brw_tracked_state brw_polygon_stipple_offset = {
/**********************************************************************
* AA Line parameters
*/
static void upload_aa_line_parameters(struct brw_context *brw)
static int upload_aa_line_parameters(struct brw_context *brw)
{
struct brw_aa_line_parameters balp;
if (BRW_IS_965(brw))
return;
return 0;
/* use legacy aa line coverage computation */
memset(&balp, 0, sizeof(balp));
@@ -365,6 +353,7 @@ static void upload_aa_line_parameters(struct brw_context *brw)
balp.header.length = sizeof(balp) / 4 - 2;
BRW_CACHED_BATCH_STRUCT(brw, &balp);
return 0;
}
const struct brw_tracked_state brw_aa_line_parameters = {
@@ -380,31 +369,16 @@ const struct brw_tracked_state brw_aa_line_parameters = {
* Line stipple packet
*/
static void upload_line_stipple(struct brw_context *brw)
static int upload_line_stipple(struct brw_context *brw)
{
struct brw_line_stipple bls;
GLfloat tmp;
GLint tmpi;
memset(&bls, 0, sizeof(bls));
bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
bls.header.length = sizeof(bls)/4 - 2;
bls.bits0.pattern = ctx->Line.StipplePattern;
bls.bits1.repeat_count = ctx->Line.StippleFactor;
tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
tmpi = tmp * (1<<13);
bls.bits1.inverse_repeat_count = tmpi;
BRW_CACHED_BATCH_STRUCT(brw, &bls);
struct brw_line_stipple *bls = NULL; //brw->curr.rast->bls;
BRW_CACHED_BATCH_STRUCT(brw, bls);
return 0;
}
const struct brw_tracked_state brw_line_stipple = {
.dirty = {
.mesa = _NEW_LINE,
.mesa = PIPE_NEW_RAST,
.brw = 0,
.cache = 0
},
@@ -416,7 +390,7 @@ const struct brw_tracked_state brw_line_stipple = {
* Misc invarient state packets
*/
static void upload_invarient_state( struct brw_context *brw )
static int upload_invarient_state( struct brw_context *brw )
{
{
/* 0x61040000 Pipeline Select */
@@ -424,7 +398,10 @@ static void upload_invarient_state( struct brw_context *brw )
struct brw_pipeline_select ps;
memset(&ps, 0, sizeof(ps));
ps.header.opcode = CMD_PIPELINE_SELECT(brw);
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
ps.header.opcode = CMD_PIPELINE_SELECT_GM45;
else
ps.header.opcode = CMD_PIPELINE_SELECT_965;
ps.header.pipeline_select = 0;
BRW_BATCH_STRUCT(brw, &ps);
}
@@ -460,12 +437,18 @@ static void upload_invarient_state( struct brw_context *brw )
struct brw_vf_statistics vfs;
memset(&vfs, 0, sizeof(vfs));
vfs.opcode = CMD_VF_STATISTICS(brw);
if (INTEL_DEBUG & DEBUG_STATS)
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
vfs.opcode = CMD_VF_STATISTICS_GM45;
else
vfs.opcode = CMD_VF_STATISTICS_965;
if (BRW_DEBUG & DEBUG_STATS)
vfs.statistics_enable = 1;
BRW_BATCH_STRUCT(brw, &vfs);
}
return 0;
}
const struct brw_tracked_state brw_invarient_state = {
@@ -485,7 +468,7 @@ const struct brw_tracked_state brw_invarient_state = {
* state pools. This comes at the expense of memory, and more expensive cache
* misses.
*/
static void upload_state_base_address( struct brw_context *brw )
static int upload_state_base_address( struct brw_context *brw )
{
/* Output the structure (brw_state_base_address) directly to the
* batchbuffer, so we can emit relocations inline.
@@ -511,6 +494,7 @@ static void upload_state_base_address( struct brw_context *brw )
OUT_BATCH(1); /* Indirect object upper bound */
ADVANCE_BATCH();
}
return 0;
}
const struct brw_tracked_state brw_state_base_address = {
src/gallium/drivers/i965/brw_pipe_blend.c
+19
View File
@@ -43,3 +43,22 @@
if (INTEL_DEBUG & DEBUG_STATS)
cc.cc5.statistics_enable = 1;
}
static void brw_set_blend_color(struct pipe_context *pipe,
const float *blend_color)
{
struct brw_context *brw = brw_context(pipe);
struct brw_blend_constant_color *bcc = &brw->curr.blend_color.bcc;
memset(bcc, 0, sizeof(*bcc));
bcc->header.opcode = CMD_BLEND_CONSTANT_COLOR;
bcc->header.length = sizeof(*bcc)/4-2;
bcc->blend_constant_color[0] = blend_color[0];
bcc->blend_constant_color[1] = blend_color[1];
bcc->blend_constant_color[2] = blend_color[2];
bcc->blend_constant_color[3] = blend_color[3];
brw->state.dirty.pipe |= PIPE_NEW_BLEND_COLOR;
}
src/gallium/drivers/i965/brw_pipe_rast.c
+20
View File
@@ -44,3 +44,23 @@ calculate_clip_key_rast()
}
}
}
static void
calculate_line_stipple_rast()
{
GLfloat tmp;
GLint tmpi;
memset(&bls, 0, sizeof(bls));
bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
bls.header.length = sizeof(bls)/4 - 2;
bls.bits0.pattern = brw->curr.rast.line_stipple_pattern;
bls.bits1.repeat_count = brw->curr.rast.line_stipple_factor + 1;
tmp = 1.0 / (GLfloat) bls.bits1.repeat_count;
tmpi = tmp * (1<<13);
bls.bits1.inverse_repeat_count = tmpi;
}
src/gallium/drivers/i965/brw_screen.h
+7
View File
@@ -95,4 +95,11 @@ brw_buffer_is_user_buffer( const struct pipe_buffer *buf )
return ((const struct brw_buffer *)buf)->is_user_buffer;
}
struct brw_winsys_buffer *
brw_surface_bo( struct pipe_surface *surface );
unsigned
brw_surface_pitch( const struct pipe_surface *surface );
#endif /* BRW_SCREEN_H */
src/gallium/drivers/i965/brw_sf.c
+1 -1
View File
@@ -131,7 +131,7 @@ static void upload_sf_prog(struct brw_context *brw)
/* Populate the key, noting state dependencies:
*/
/* CACHE_NEW_VS_PROG */
key.attrs = brw->vs.prog_data->outputs_written;
key.attrs = brw->vs.prog_data->nr_outputs_written;
/* BRW_NEW_REDUCED_PRIMITIVE */
switch (brw->reduced_primitive) {
src/gallium/drivers/i965/brw_state.h
+3 -1
View File
@@ -33,9 +33,11 @@
#ifndef BRW_STATE_H
#define BRW_STATE_H
#include "brw_context.h"
#include "pipe/p_error.h"
#include "util/u_memory.h"
#include "brw_context.h"
static inline void
brw_add_validated_bo(struct brw_context *brw, struct brw_winsys_buffer *bo)
{
src/gallium/drivers/i965/brw_urb.c
+2 -1
View File
@@ -221,7 +221,7 @@ const struct brw_tracked_state brw_recalculate_urb_fence = {
void brw_upload_urb_fence(struct brw_context *brw)
int brw_upload_urb_fence(struct brw_context *brw)
{
struct brw_urb_fence uf;
memset(&uf, 0, sizeof(uf));
@@ -247,4 +247,5 @@ void brw_upload_urb_fence(struct brw_context *brw)
uf.bits1.cs_fence = URB_SIZES(brw);
BRW_BATCH_STRUCT(brw, &uf);
return 0;
}
src/gallium/drivers/i965/brw_vs.c
+2 -2
View File
@@ -51,11 +51,11 @@ static void do_vs_prog( struct brw_context *brw,
brw_init_compile(brw, &c.func);
c.vp = vp;
c.prog_data.outputs_written = vp->program.Base.OutputsWritten;
c.prog_data.nr_outputs_written = vp->program.Base.OutputsWritten;
c.prog_data.inputs_read = vp->program.Base.InputsRead;
if (c.key.copy_edgeflag) {
c.prog_data.outputs_written |= 1<<VERT_RESULT_EDGE;
c.prog_data.nr_outputs_written |= 1<<VERT_RESULT_EDGE;
c.prog_data.inputs_read |= 1<<VERT_ATTRIB_EDGEFLAG;
}
src/gallium/drivers/i965/brw_vs_emit.c
+33 -36
View File
@@ -140,35 +140,33 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
c->first_overflow_output = 0;
if (BRW_IS_IGDNG(c->func.brw))
mrf = 8;
mrf = 8;
else
mrf = 4;
mrf = 4;
for (i = 0; i < VERT_RESULT_MAX; i++) {
if (c->prog_data.outputs_written & (1 << i)) {
c->nr_outputs++;
assert(i < Elements(c->regs[PROGRAM_OUTPUT]));
if (i == VERT_RESULT_HPOS) {
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
}
else if (i == VERT_RESULT_PSIZ) {
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
mrf++; /* just a placeholder? XXX fix later stages & remove this */
for (i = 0; i < c->prog_data.nr_outputs_written; i++) {
c->nr_outputs++;
assert(i < Elements(c->regs[PROGRAM_OUTPUT]));
if (i == VERT_RESULT_HPOS) {
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
}
else if (i == VERT_RESULT_PSIZ) {
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
mrf++; /* just a placeholder? XXX fix later stages & remove this */
}
else {
if (mrf < 16) {
c->regs[PROGRAM_OUTPUT][i] = brw_message_reg(mrf);
mrf++;
}
else {
if (mrf < 16) {
c->regs[PROGRAM_OUTPUT][i] = brw_message_reg(mrf);
mrf++;
}
else {
/* too many vertex results to fit in MRF, use GRF for overflow */
if (!c->first_overflow_output)
c->first_overflow_output = i;
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
}
/* too many vertex results to fit in MRF, use GRF for overflow */
if (!c->first_overflow_output)
c->first_overflow_output = i;
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
}
}
}
@@ -238,9 +236,9 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
if (BRW_IS_IGDNG(c->func.brw))
c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
else
c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
c->prog_data.total_grf = reg;
@@ -1050,8 +1048,9 @@ static void emit_vertex_write( struct brw_vs_compile *c)
/* Update the header for point size, user clipping flags, and -ve rhw
* workaround.
*/
if ((c->prog_data.outputs_written & (1<<VERT_RESULT_PSIZ)) ||
c->key.nr_userclip || BRW_IS_965(p->brw))
if (c->prog_data.writes_psiz ||
c->key.nr_userclip ||
BRW_IS_965(p->brw))
{
struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
GLuint i;
@@ -1060,7 +1059,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
brw_set_access_mode(p, BRW_ALIGN_16);
if (c->prog_data.outputs_written & (1<<VERT_RESULT_PSIZ)) {
if (c->prog_data.writes_psiz) {
struct brw_reg psiz = c->regs[PROGRAM_OUTPUT][VERT_RESULT_PSIZ];
brw_MUL(p, brw_writemask(header1, BRW_WRITEMASK_W), brw_swizzle1(psiz, 0), brw_imm_f(1<<11));
brw_AND(p, brw_writemask(header1, BRW_WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8));
@@ -1149,12 +1148,10 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* at mrf[4] atm...
*/
GLuint i, mrf = 0;
for (i = c->first_overflow_output; i < VERT_RESULT_MAX; i++) {
if (c->prog_data.outputs_written & (1 << i)) {
/* move from GRF to MRF */
brw_MOV(p, brw_message_reg(4+mrf), c->regs[PROGRAM_OUTPUT][i]);
mrf++;
}
for (i = c->first_overflow_output; i < c->prog_data.nr_outputs_written; i++) {
/* move from GRF to MRF */
brw_MOV(p, brw_message_reg(4+mrf), c->regs[PROGRAM_OUTPUT][i]);
mrf++;
}
brw_urb_WRITE(p,
src/gallium/drivers/i965/brw_wm.c
+1 -1
View File
@@ -310,7 +310,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
}
/* CACHE_NEW_VS_PROG */
key->vp_outputs_written = brw->vs.prog_data->outputs_written; /* bitmask */
key->vp_nr_outputs_written = brw->vs.prog_data->nr_outputs_written;
/* The unique fragment program ID */
key->program_string_id = fp->id;
src/gallium/drivers/i965/brw_wm.h
+1 -1
View File
@@ -76,7 +76,7 @@ struct brw_wm_prog_key {
GLuint program_string_id:32;
GLuint drawable_height;
GLuint vp_outputs_written;
GLuint vp_nr_outputs_written;
};