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etnaviv: isa: Add tg4 instruction

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This instruction is used to implement textureGather.

Blob generates such tex_gather's for dEQP-GLES31.functional.texture.gather.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36622>
This commit is contained in:
Christian Gmeiner
2025-05-23 13:23:11 +02:00
committed by Marge Bot
parent aa91ece579
commit 561faa2259
2 changed files with 45 additions and 0 deletions
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src/etnaviv/isa/etnaviv.xml
+44
View File
@@ -748,6 +748,45 @@ SPDX-License-Identifier: MIT
<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
</bitset>
<bitset name="#instruction-tex-src0-src1" extends="#instruction-tex">
<meta has_dest="true" valid_srcs="0|1"/>
<display>
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, {SRC1}, void
</display>
<!-- SRC0 -->
<pattern pos="43">1</pattern> <!-- SRC0_USE -->
<field name="SRC0_REG" low="44" high="52" type="uint"/>
<field name="SRC0" low="54" high="63" type="#instruction-src">
<param name="SRC0_REG" as="SRC_REG"/>
<param name="SRC0_AMODE" as="SRC_AMODE"/>
<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
</field>
<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
<!-- SRC1 -->
<pattern pos="70">1</pattern> <!-- SRC1_USE -->
<field name="SRC1_REG" low="71" high="79" type="uint"/>
<field name="SRC1" low="81" high="90" type="#instruction-src">
<param name="SRC1_REG" as="SRC_REG"/>
<param name="SRC1_AMODE" as="SRC_AMODE"/>
<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
</field>
<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
<!-- SRC2 -->
<pattern pos="99">0</pattern> <!-- SRC2_USE -->
<pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG -->
<pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ -->
<pattern pos="118">0</pattern> <!-- SRC2_NEG -->
<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
</bitset>
<bitset name="#instruction-tex-src0-src1-src2" extends="#instruction-tex">
<meta has_dest="true" valid_srcs="0|1|2"/>
@@ -1531,6 +1570,11 @@ SPDX-License-Identifier: MIT
<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="tg4" extends="#instruction-tex-src0-src1">
<pattern low="0" high="5">111101</pattern> <!-- OPC -->
<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="#extended-instruction-alu" extends="#instruction-alu">
<pattern low="0" high="5">111111</pattern> <!-- OPC -->
<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
src/etnaviv/isa/tests/disasm.cpp
+1
View File
@@ -200,6 +200,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
disasm_state{ {0x00821036, 0x0e401804, 0x00010000, 0x00000000}, "norm_dp4 t2.x___, t1.yzwx, void, void\n"},
disasm_state{ {0x07801039, 0x39204c00, 0x80a90050, 0x00000000}, "img_load.denorm.u32.pack t0, u4.xyzw, t0.xyyy, void\n"},
disasm_state{ {0x0780083a, 0x39200c00, 0x80a90050, 0x00390018}, "img_store.sat.denorm.u32.pack mem, u0.xyzw, t0.xyyy, t1.xyzw\n"},
disasm_state{ {0x0781103d, 0x15001f20, 0x100101c0, 0x00000007}, "tg4 t1, tex0.xyzw, t1.xyyy, 3, void\n"},
disasm_state{ {0x0381103f, 0x29201804, 0x80010000, 0x780000b8}, "bit_findlsb.u32 t1.xyz_, t1.xyzz, void, void\n"},
disasm_state{ {0x0081103f, 0x00001804, 0x40010000, 0x780000c8}, "bit_findmsb.s32 t1.x___, t1.xxxx, void, void\n"}
)