AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

treewide: Remove remaining nir_ssa_for_src

Browse Source 
Coccinelle missed these, a few manual changes here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25247>
This commit is contained in:
Alyssa Rosenzweig
2023-09-15 11:05:15 -04:00
parent d1eb17e92e
commit 55333fce77
3 changed files with 7 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/compiler/nir/nir_lower_system_values.c
+1 -2
View File
@@ -166,12 +166,11 @@ lower_system_value_instr(nir_builder *b, nir_instr *instr, void *_state)
switch (deref->var->data.location) {
case SYSTEM_VALUE_TESS_LEVEL_INNER:
case SYSTEM_VALUE_TESS_LEVEL_OUTER: {
nir_def *index = nir_ssa_for_src(b, arr_deref->arr.index, 1);
nir_def *sysval = (deref->var->data.location ==
SYSTEM_VALUE_TESS_LEVEL_INNER)
? nir_load_tess_level_inner(b)
: nir_load_tess_level_outer(b);
return nir_vector_extract(b, sysval, index);
return nir_vector_extract(b, sysval, arr_deref->arr.index.ssa);
}
case SYSTEM_VALUE_SAMPLE_MASK_IN:
src/freedreno/ir3/ir3_nir_lower_64b.c
+2 -3
View File
@@ -258,13 +258,12 @@ lower_64b_global(nir_builder *b, nir_instr *instr, void *unused)
if (intr->intrinsic == nir_intrinsic_global_atomic) {
return nir_global_atomic_ir3(
b, intr->def.bit_size, addr,
nir_ssa_for_src(b, intr->src[1], 1),
intr->src[1].ssa,
.atomic_op = nir_intrinsic_atomic_op(intr));
} else if (intr->intrinsic == nir_intrinsic_global_atomic_swap) {
return nir_global_atomic_swap_ir3(
b, intr->def.bit_size, addr,
nir_ssa_for_src(b, intr->src[1], 1),
nir_ssa_for_src(b, intr->src[2], 1),
intr->src[1].ssa, intr->src[2].ssa,
.atomic_op = nir_intrinsic_atomic_op(intr));
}
src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp
+4 -4
View File
@@ -188,12 +188,12 @@ class LowerSplit64op : public NirLowerInstruction {
case nir_op_bcsel: {
auto lo =
nir_bcsel(b,
nir_ssa_for_src(b, alu->src[0].src, 1),
alu->src[0].src.ssa,
nir_unpack_64_2x32_split_x(b, nir_ssa_for_alu_src(b, alu, 1)),
nir_unpack_64_2x32_split_x(b, nir_ssa_for_alu_src(b, alu, 2)));
auto hi =
nir_bcsel(b,
nir_ssa_for_src(b, alu->src[0].src, 1),
alu->src[0].src.ssa,
nir_unpack_64_2x32_split_y(b, nir_ssa_for_alu_src(b, alu, 1)),
nir_unpack_64_2x32_split_y(b, nir_ssa_for_alu_src(b, alu, 2)));
return nir_pack_64_2x32_split(b, lo, hi);
@@ -253,8 +253,8 @@ class LowerSplit64op : public NirLowerInstruction {
&phi_hi->instr, &phi_hi->def, phi->def.num_components * 2, 32);
nir_foreach_phi_src(s, phi)
{
auto lo = nir_unpack_32_2x16_split_x(b, nir_ssa_for_src(b, s->src, 1));
auto hi = nir_unpack_32_2x16_split_x(b, nir_ssa_for_src(b, s->src, 1));
auto lo = nir_unpack_32_2x16_split_x(b, s->src.ssa);
auto hi = nir_unpack_32_2x16_split_x(b, s->src.ssa);
nir_phi_instr_add_src(phi_lo, s->pred, lo);
nir_phi_instr_add_src(phi_hi, s->pred, hi);
}