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radv: avoid providing an align_mul to intrinsic builders

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14455>
This commit is contained in:
Rhys Perry
2022-01-07 16:06:04 +00:00
committed by Marge Bot
parent 7833759a41
commit 552e59aee3
5 changed files with 85 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_acceleration_structure.c
+61 -74
View File
@@ -722,7 +722,7 @@ get_indices(nir_builder *b, nir_ssa_def *addr, nir_ssa_def *type, nir_ssa_def *i
for (unsigned i = 0; i < 3; ++i) {
indices[i] = nir_build_load_global(
b, 1, 16, nir_iadd(b, addr, nir_u2u64(b, nir_iadd(b, index_id, nir_imm_int(b, 2 * i)))),
.align_mul = 2, .align_offset = 0);
.align_offset = 0);
}
nir_store_var(b, result, nir_u2u32(b, nir_vec(b, indices, 3)), 7);
}
@@ -730,7 +730,7 @@ get_indices(nir_builder *b, nir_ssa_def *addr, nir_ssa_def *type, nir_ssa_def *i
{
nir_ssa_def *index_id = nir_umul24(b, id, nir_imm_int(b, 12));
nir_ssa_def *indices = nir_build_load_global(
b, 3, 32, nir_iadd(b, addr, nir_u2u64(b, index_id)), .align_mul = 4, .align_offset = 0);
b, 3, 32, nir_iadd(b, addr, nir_u2u64(b, index_id)), .align_offset = 0);
nir_store_var(b, result, indices, 7);
}
nir_pop_if(b, NULL);
@@ -751,7 +751,7 @@ get_indices(nir_builder *b, nir_ssa_def *addr, nir_ssa_def *type, nir_ssa_def *i
{
for (unsigned i = 0; i < 3; ++i) {
indices[i] = nir_build_load_global(b, 1, 8, nir_iadd(b, addr, nir_u2u64(b, indices[i])),
.align_mul = 1, .align_offset = 0);
.align_offset = 0);
}
nir_store_var(b, result, nir_u2u32(b, nir_vec(b, indices, 3)), 7);
}
@@ -784,10 +784,9 @@ get_vertices(nir_builder *b, nir_ssa_def *addresses, nir_ssa_def *format, nir_ss
switch (formats[f]) {
case VK_FORMAT_R32G32B32_SFLOAT:
case VK_FORMAT_R32G32B32A32_SFLOAT:
nir_store_var(b, results[i],
nir_build_load_global(b, 3, 32, nir_channel(b, addresses, i),
.align_mul = 4, .align_offset = 0),
7);
nir_store_var(
b, results[i],
nir_build_load_global(b, 3, 32, nir_channel(b, addresses, i), .align_offset = 0), 7);
break;
case VK_FORMAT_R32G32_SFLOAT:
case VK_FORMAT_R16G16_SFLOAT:
@@ -805,7 +804,7 @@ get_vertices(nir_builder *b, nir_ssa_def *addresses, nir_ssa_def *format, nir_ss
for (unsigned j = 0; j < components; ++j)
values[j] = nir_build_load_global(
b, 1, comp_bits, nir_iadd(b, addr, nir_imm_int64(b, j * comp_bytes)),
.align_mul = comp_bytes, .align_offset = 0);
.align_offset = 0);
for (unsigned j = components; j < 3; ++j)
values[j] = nir_imm_intN_t(b, 0, comp_bits);
@@ -984,17 +983,17 @@ build_leaf_shader(struct radv_device *dev)
nir_store_var(
&b, transform[0],
nir_build_load_global(&b, 4, 32, nir_iadd(&b, transform_addr, nir_imm_int64(&b, 0)),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
0xf);
nir_store_var(
&b, transform[1],
nir_build_load_global(&b, 4, 32, nir_iadd(&b, transform_addr, nir_imm_int64(&b, 16)),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
0xf);
nir_store_var(
&b, transform[2],
nir_build_load_global(&b, 4, 32, nir_iadd(&b, transform_addr, nir_imm_int64(&b, 32)),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
0xf);
nir_pop_if(&b, NULL);
@@ -1016,7 +1015,7 @@ build_leaf_shader(struct radv_device *dev)
}
nir_ssa_def *node_id = nir_ushr(&b, node_offset, nir_imm_int(&b, 3));
nir_build_store_global(&b, node_id, scratch_addr, .align_mul = 4, .align_offset = 0);
nir_build_store_global(&b, node_id, scratch_addr, .align_offset = 0);
}
nir_push_else(&b, NULL);
nir_push_if(&b, nir_ieq(&b, geom_type, nir_imm_int(&b, VK_GEOMETRY_TYPE_AABBS_KHR)));
@@ -1029,16 +1028,14 @@ build_leaf_shader(struct radv_device *dev)
nir_ssa_def *aabb_node_dst_addr = nir_iadd(&b, node_dst_addr, nir_u2u64(&b, node_offset));
nir_ssa_def *node_id =
nir_iadd(&b, nir_ushr(&b, node_offset, nir_imm_int(&b, 3)), nir_imm_int(&b, 7));
nir_build_store_global(&b, node_id, scratch_addr, .align_mul = 4, .align_offset = 0);
nir_build_store_global(&b, node_id, scratch_addr, .align_offset = 0);
aabb_addr = nir_iadd(&b, aabb_addr, nir_u2u64(&b, nir_imul(&b, aabb_stride, global_id)));
nir_ssa_def *min_bound =
nir_build_load_global(&b, 3, 32, nir_iadd(&b, aabb_addr, nir_imm_int64(&b, 0)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *max_bound =
nir_build_load_global(&b, 3, 32, nir_iadd(&b, aabb_addr, nir_imm_int64(&b, 12)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *min_bound = nir_build_load_global(
&b, 3, 32, nir_iadd(&b, aabb_addr, nir_imm_int64(&b, 0)), .align_offset = 0);
nir_ssa_def *max_bound = nir_build_load_global(
&b, 3, 32, nir_iadd(&b, aabb_addr, nir_imm_int64(&b, 12)), .align_offset = 0);
nir_ssa_def *values[] = {nir_channel(&b, min_bound, 0),
nir_channel(&b, min_bound, 1),
@@ -1080,21 +1077,20 @@ build_leaf_shader(struct radv_device *dev)
nir_ssa_def *inst_transform[] = {
nir_build_load_global(&b, 4, 32, nir_iadd(&b, instance_addr, nir_imm_int64(&b, 0)),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
nir_build_load_global(&b, 4, 32, nir_iadd(&b, instance_addr, nir_imm_int64(&b, 16)),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
nir_build_load_global(&b, 4, 32, nir_iadd(&b, instance_addr, nir_imm_int64(&b, 32)),
.align_mul = 4, .align_offset = 0)};
nir_ssa_def *inst3 =
nir_build_load_global(&b, 4, 32, nir_iadd(&b, instance_addr, nir_imm_int64(&b, 48)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0)};
nir_ssa_def *inst3 = nir_build_load_global(
&b, 4, 32, nir_iadd(&b, instance_addr, nir_imm_int64(&b, 48)), .align_offset = 0);
nir_ssa_def *node_offset =
nir_iadd(&b, node_dst_offset, nir_umul24(&b, global_id, nir_imm_int(&b, 128)));
node_dst_addr = nir_iadd(&b, node_dst_addr, nir_u2u64(&b, node_offset));
nir_ssa_def *node_id =
nir_iadd(&b, nir_ushr(&b, node_offset, nir_imm_int(&b, 3)), nir_imm_int(&b, 6));
nir_build_store_global(&b, node_id, scratch_addr, .align_mul = 4, .align_offset = 0);
nir_build_store_global(&b, node_id, scratch_addr, .align_offset = 0);
nir_variable *bounds[2] = {
nir_variable_create(b.shader, nir_var_shader_temp, vec3_type, "min_bound"),
@@ -1106,15 +1102,12 @@ build_leaf_shader(struct radv_device *dev)
nir_ssa_def *header_addr = nir_pack_64_2x32(&b, nir_channels(&b, inst3, 12));
nir_push_if(&b, nir_ine(&b, header_addr, nir_imm_int64(&b, 0)));
nir_ssa_def *header_root_offset =
nir_build_load_global(&b, 1, 32, nir_iadd(&b, header_addr, nir_imm_int64(&b, 0)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *header_min =
nir_build_load_global(&b, 3, 32, nir_iadd(&b, header_addr, nir_imm_int64(&b, 8)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *header_max =
nir_build_load_global(&b, 3, 32, nir_iadd(&b, header_addr, nir_imm_int64(&b, 20)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *header_root_offset = nir_build_load_global(
&b, 1, 32, nir_iadd(&b, header_addr, nir_imm_int64(&b, 0)), .align_offset = 0);
nir_ssa_def *header_min = nir_build_load_global(
&b, 3, 32, nir_iadd(&b, header_addr, nir_imm_int64(&b, 8)), .align_offset = 0);
nir_ssa_def *header_max = nir_build_load_global(
&b, 3, 32, nir_iadd(&b, header_addr, nir_imm_int64(&b, 20)), .align_offset = 0);
nir_ssa_def *bound_defs[2][3];
for (unsigned i = 0; i < 3; ++i) {
@@ -1141,7 +1134,7 @@ build_leaf_shader(struct radv_device *dev)
nir_build_store_global(&b, nir_vec(&b, vals, 3),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 92 + 12 * i)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
}
nir_ssa_def *m_in[3][3], *m_out[3][3], *m_vec[3][4];
@@ -1158,7 +1151,7 @@ build_leaf_shader(struct radv_device *dev)
for (unsigned i = 0; i < 3; ++i) {
nir_build_store_global(&b, nir_vec(&b, m_vec[i], 4),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 16 + 16 * i)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
}
nir_ssa_def *out0[4] = {
@@ -1166,17 +1159,14 @@ build_leaf_shader(struct radv_device *dev)
nir_channel(&b, nir_unpack_64_2x32(&b, header_addr), 1), nir_channel(&b, inst3, 0),
nir_channel(&b, inst3, 1)};
nir_build_store_global(&b, nir_vec(&b, out0, 4),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 0)), .align_mul = 4,
.align_offset = 0);
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 0)), .align_offset = 0);
nir_build_store_global(&b, global_id, nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 88)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_pop_if(&b, NULL);
nir_build_store_global(&b, nir_load_var(&b, bounds[0]),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 64)), .align_mul = 4,
.align_offset = 0);
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 64)), .align_offset = 0);
nir_build_store_global(&b, nir_load_var(&b, bounds[1]),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 76)), .align_mul = 4,
.align_offset = 0);
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 76)), .align_offset = 0);
}
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@@ -1197,9 +1187,8 @@ determine_bounds(nir_builder *b, nir_ssa_def *node_addr, nir_ssa_def *node_id,
{
nir_ssa_def *positions[3];
for (unsigned i = 0; i < 3; ++i)
positions[i] =
nir_build_load_global(b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, i * 12)),
.align_mul = 4, .align_offset = 0);
positions[i] = nir_build_load_global(
b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, i * 12)), .align_offset = 0);
nir_ssa_def *bounds[] = {positions[0], positions[0]};
for (unsigned i = 1; i < 3; ++i) {
bounds[0] = nir_fmin(b, bounds[0], positions[i]);
@@ -1216,7 +1205,7 @@ determine_bounds(nir_builder *b, nir_ssa_def *node_addr, nir_ssa_def *node_id,
for (unsigned j = 0; j < 2; ++j)
input_bounds[i][j] = nir_build_load_global(
b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 16 + i * 24 + j * 12)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_ssa_def *bounds[] = {input_bounds[0][0], input_bounds[0][1]};
for (unsigned i = 1; i < 4; ++i) {
bounds[0] = nir_fmin(b, bounds[0], input_bounds[i][0]);
@@ -1231,9 +1220,8 @@ determine_bounds(nir_builder *b, nir_ssa_def *node_addr, nir_ssa_def *node_id,
{ /* Instances */
nir_ssa_def *bounds[2];
for (unsigned i = 0; i < 2; ++i)
bounds[i] =
nir_build_load_global(b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 64 + i * 12)),
.align_mul = 4, .align_offset = 0);
bounds[i] = nir_build_load_global(
b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 64 + i * 12)), .align_offset = 0);
nir_store_var(b, bounds_vars[0], bounds[0], 7);
nir_store_var(b, bounds_vars[1], bounds[1], 7);
}
@@ -1241,9 +1229,8 @@ determine_bounds(nir_builder *b, nir_ssa_def *node_addr, nir_ssa_def *node_id,
{ /* AABBs */
nir_ssa_def *bounds[2];
for (unsigned i = 0; i < 2; ++i)
bounds[i] =
nir_build_load_global(b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, i * 12)),
.align_mul = 4, .align_offset = 0);
bounds[i] = nir_build_load_global(
b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, i * 12)), .align_offset = 0);
nir_store_var(b, bounds_vars[0], bounds[0], 7);
nir_store_var(b, bounds_vars[1], bounds[1], 7);
}
@@ -1301,10 +1288,10 @@ build_internal_shader(struct radv_device *dev)
nir_iadd(&b, scratch_addr,
nir_u2u64(&b, nir_iadd(&b, src_scratch_offset,
nir_ishl(&b, global_id, nir_imm_int(&b, 4))))),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_build_store_global(&b, src_nodes, nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 0)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_ssa_def *total_bounds[2] = {
nir_channels(&b, nir_imm_vec4(&b, NAN, NAN, NAN, NAN), 7),
@@ -1324,10 +1311,10 @@ build_internal_shader(struct radv_device *dev)
nir_pop_if(&b, NULL);
nir_build_store_global(&b, nir_load_var(&b, bounds[0]),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 16 + 24 * i)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_build_store_global(&b, nir_load_var(&b, bounds[1]),
nir_iadd(&b, node_dst_addr, nir_imm_int64(&b, 28 + 24 * i)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
total_bounds[0] = nir_fmin(&b, total_bounds[0], nir_load_var(&b, bounds[0]));
total_bounds[1] = nir_fmax(&b, total_bounds[1], nir_load_var(&b, bounds[1]));
}
@@ -1337,14 +1324,14 @@ build_internal_shader(struct radv_device *dev)
nir_ssa_def *dst_scratch_addr = nir_iadd(
&b, scratch_addr,
nir_u2u64(&b, nir_iadd(&b, dst_scratch_offset, nir_ishl(&b, global_id, nir_imm_int(&b, 2)))));
nir_build_store_global(&b, node_id, dst_scratch_addr, .align_mul = 4, .align_offset = 0);
nir_build_store_global(&b, node_id, dst_scratch_addr, .align_offset = 0);
nir_push_if(&b, fill_header);
nir_build_store_global(&b, node_id, node_addr, .align_mul = 4, .align_offset = 0);
nir_build_store_global(&b, node_id, node_addr, .align_offset = 0);
nir_build_store_global(&b, total_bounds[0], nir_iadd(&b, node_addr, nir_imm_int64(&b, 8)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_build_store_global(&b, total_bounds[1], nir_iadd(&b, node_addr, nir_imm_int64(&b, 20)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_pop_if(&b, NULL);
return b.shader;
}
@@ -1411,17 +1398,17 @@ build_copy_shader(struct radv_device *dev)
&b, 1, 32,
nir_iadd(&b, src_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, instance_count))),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_ssa_def *compacted_size = nir_build_load_global(
&b, 1, 64,
nir_iadd(&b, src_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, compacted_size))),
.align_mul = 8, .align_offset = 0);
.align_offset = 0);
nir_ssa_def *serialization_size = nir_build_load_global(
&b, 1, 64,
nir_iadd(&b, src_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, serialization_size))),
.align_mul = 8, .align_offset = 0);
.align_offset = 0);
nir_store_var(&b, compacted_size_var, compacted_size, 1);
nir_store_var(
@@ -1430,7 +1417,7 @@ build_copy_shader(struct radv_device *dev)
&b, 1, 32,
nir_iadd(&b, src_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, instance_offset))),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
1);
nir_store_var(&b, instance_count_var, instance_count, 1);
@@ -1447,19 +1434,19 @@ build_copy_shader(struct radv_device *dev)
nir_iadd(&b, dst_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_serialization_header,
serialization_size))),
.align_mul = 8, .align_offset = 0);
.align_offset = 0);
nir_build_store_global(
&b, compacted_size,
nir_iadd(&b, dst_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_serialization_header,
compacted_size))),
.align_mul = 8, .align_offset = 0);
.align_offset = 0);
nir_build_store_global(
&b, nir_u2u64(&b, instance_count),
nir_iadd(&b, dst_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_serialization_header,
instance_count))),
.align_mul = 8, .align_offset = 0);
.align_offset = 0);
}
nir_pop_if(&b, NULL);
}
@@ -1471,7 +1458,7 @@ build_copy_shader(struct radv_device *dev)
nir_iadd(&b, src_base_addr,
nir_imm_int64(
&b, offsetof(struct radv_accel_struct_serialization_header, instance_count))),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_ssa_def *src_offset =
nir_iadd(&b, nir_imm_int(&b, sizeof(struct radv_accel_struct_serialization_header)),
nir_imul(&b, instance_count, nir_imm_int(&b, sizeof(uint64_t))));
@@ -1483,7 +1470,7 @@ build_copy_shader(struct radv_device *dev)
&b, 1, 64,
nir_iadd(&b, header_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, compacted_size))),
.align_mul = 8, .align_offset = 0),
.align_offset = 0),
1);
nir_store_var(
&b, instance_offset_var,
@@ -1491,7 +1478,7 @@ build_copy_shader(struct radv_device *dev)
&b, 1, 32,
nir_iadd(&b, header_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, instance_offset))),
.align_mul = 4, .align_offset = 0),
.align_offset = 0),
1);
nir_store_var(&b, instance_count_var, instance_count, 1);
nir_store_var(&b, src_offset_var, src_offset, 1);
@@ -1505,7 +1492,7 @@ build_copy_shader(struct radv_device *dev)
&b, 1, 64,
nir_iadd(&b, src_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, compacted_size))),
.align_mul = 8, .align_offset = 0),
.align_offset = 0),
1);
nir_store_var(&b, src_offset_var, nir_imm_int(&b, 0), 1);
@@ -1523,7 +1510,7 @@ build_copy_shader(struct radv_device *dev)
&b, 1, 32,
nir_iadd(&b, src_base_addr,
nir_imm_int64(&b, offsetof(struct radv_accel_struct_header, compacted_size))),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_push_loop(&b);
{
src/amd/vulkan/radv_meta_copy_vrs_htile.c
+2 -3
View File
@@ -118,7 +118,7 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
nir_push_if(&b, nir_ieq(&b, read_htile_value, nir_imm_int(&b, 1)));
{
/* Load the existing HTILE 32-bit value for this 8x8 pixels area. */
nir_ssa_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr, .align_mul = 4);
nir_ssa_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr);
/* Clear the 4-bit VRS rates. */
nir_store_var(&b, htile_value, nir_iand(&b, input_value, nir_imm_int(&b, 0xfffff33f)), 0x1);
@@ -133,8 +133,7 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
nir_ssa_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates);
/* Store the updated HTILE 32-bit which contains the VRS rates. */
nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .access = ACCESS_NON_READABLE,
.align_mul = 4);
nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .access = ACCESS_NON_READABLE);
return b.shader;
}
src/amd/vulkan/radv_pipeline_rt.c
+9 -12
View File
@@ -348,8 +348,7 @@ load_sbt_entry(nir_builder *b, const struct rt_variables *vars, nir_ssa_def *idx
nir_ssa_def *load_addr = addr;
if (offset)
load_addr = nir_iadd(b, load_addr, nir_imm_int64(b, offset));
nir_ssa_def *v_idx =
nir_build_load_global(b, 1, 32, load_addr, .align_mul = 4, .align_offset = 0);
nir_ssa_def *v_idx = nir_build_load_global(b, 1, 32, load_addr, .align_offset = 0);
nir_store_var(b, vars->idx, v_idx, 1);
@@ -633,7 +632,7 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
val = nir_build_load_global(
&b_shader, 3, 32,
nir_iadd(&b_shader, instance_node_addr, nir_imm_int64(&b_shader, 92 + c * 12)),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
}
b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def_rewrite_uses(&intr->dest.ssa, val);
@@ -1262,7 +1261,7 @@ insert_traversal_triangle_case(struct radv_device *device,
b, 2, 32,
nir_iadd(b, build_node_to_addr(device, b, bvh_node),
nir_imm_int64(b, offsetof(struct radv_bvh_triangle_node, triangle_id))),
.align_mul = 4, .align_offset = 0);
.align_offset = 0);
nir_ssa_def *primitive_id = nir_channel(b, triangle_info, 0);
nir_ssa_def *geometry_id_and_flags = nir_channel(b, triangle_info, 1);
nir_ssa_def *geometry_id = nir_iand(b, geometry_id_and_flags, nir_imm_int(b, 0xfffffff));
@@ -1367,7 +1366,7 @@ insert_traversal_aabb_case(struct radv_device *device,
nir_ssa_def *node_addr = build_node_to_addr(device, b, bvh_node);
nir_ssa_def *triangle_info = nir_build_load_global(
b, 2, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 24)), .align_mul = 4, .align_offset = 0);
b, 2, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 24)), .align_offset = 0);
nir_ssa_def *primitive_id = nir_channel(b, triangle_info, 0);
nir_ssa_def *geometry_id_and_flags = nir_channel(b, triangle_info, 1);
nir_ssa_def *geometry_id = nir_iand(b, geometry_id_and_flags, nir_imm_int(b, 0xfffffff));
@@ -1444,12 +1443,10 @@ insert_traversal_aabb_case(struct radv_device *device,
nir_ssa_def *vec3_inf =
nir_channels(b, nir_imm_vec4(b, INFINITY, INFINITY, INFINITY, 0), 0x7);
nir_ssa_def *bvh_lo =
nir_build_load_global(b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 0)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *bvh_hi =
nir_build_load_global(b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 12)),
.align_mul = 4, .align_offset = 0);
nir_ssa_def *bvh_lo = nir_build_load_global(
b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 0)), .align_offset = 0);
nir_ssa_def *bvh_hi = nir_build_load_global(
b, 3, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 12)), .align_offset = 0);
bvh_lo = nir_fsub(b, bvh_lo, nir_load_var(b, trav_vars->origin));
bvh_hi = nir_fsub(b, bvh_hi, nir_load_var(b, trav_vars->origin));
@@ -1911,7 +1908,7 @@ insert_traversal(struct radv_device *device, const VkRayTracingPipelineCreateInf
nir_iadd(b, instance_node_addr, nir_imm_int64(b, 48)),
.align_mul = 64, .align_offset = 48)};
nir_ssa_def *instance_id = nir_build_load_global(
b, 1, 32, nir_iadd(b, instance_node_addr, nir_imm_int64(b, 88)), .align_mul = 4,
b, 1, 32, nir_iadd(b, instance_node_addr, nir_imm_int64(b, 88)),
.align_offset = 0);
nir_ssa_def *instance_and_mask = nir_channel(b, instance_data, 2);
nir_ssa_def *instance_mask = nir_ushr(b, instance_and_mask, nir_imm_int(b, 24));
src/amd/vulkan/radv_query.c
+12 -15
View File
@@ -67,7 +67,7 @@ radv_store_availability(nir_builder *b, nir_ssa_def *flags, nir_ssa_def *dst_buf
nir_push_else(b, NULL);
nir_store_ssbo(b, value32, dst_buf, offset, .align_mul = 4);
nir_store_ssbo(b, value32, dst_buf, offset);
nir_pop_if(b, NULL);
@@ -273,7 +273,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
avail_offset = nir_iadd(&b, avail_offset, nir_imul(&b, global_id, nir_imm_int(&b, 4)));
nir_ssa_def *available32 = nir_load_ssbo(&b, 1, 32, src_buf, avail_offset, .align_mul = 4);
nir_ssa_def *available32 = nir_load_ssbo(&b, 1, 32, src_buf, avail_offset);
nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);
nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
@@ -291,24 +291,23 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
nir_ssa_def *start_offset =
nir_iadd(&b, input_base, nir_imm_int(&b, pipeline_statistics_indices[i] * 8));
nir_ssa_def *start = nir_load_ssbo(&b, 1, 64, src_buf, start_offset, .align_mul = 8);
nir_ssa_def *start = nir_load_ssbo(&b, 1, 64, src_buf, start_offset);
nir_ssa_def *end_offset =
nir_iadd(&b, input_base,
nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size));
nir_ssa_def *end = nir_load_ssbo(&b, 1, 64, src_buf, end_offset, .align_mul = 8);
nir_ssa_def *end = nir_load_ssbo(&b, 1, 64, src_buf, end_offset);
nir_ssa_def *result = nir_isub(&b, end, start);
/* Store result */
nir_push_if(&b, result_is_64bit);
nir_store_ssbo(&b, result, dst_buf, nir_load_var(&b, output_offset), .align_mul = 8);
nir_store_ssbo(&b, result, dst_buf, nir_load_var(&b, output_offset));
nir_push_else(&b, NULL);
nir_store_ssbo(&b, nir_u2u32(&b, result), dst_buf, nir_load_var(&b, output_offset),
.align_mul = 4);
nir_store_ssbo(&b, nir_u2u32(&b, result), dst_buf, nir_load_var(&b, output_offset));
nir_pop_if(&b, NULL);
@@ -335,11 +334,11 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
nir_ssa_def *output_elem = nir_iadd(&b, output_base, nir_imul(&b, elem_size, current_counter));
nir_push_if(&b, result_is_64bit);
nir_store_ssbo(&b, nir_imm_int64(&b, 0), dst_buf, output_elem, .align_mul = 8);
nir_store_ssbo(&b, nir_imm_int64(&b, 0), dst_buf, output_elem);
nir_push_else(&b, NULL);
nir_store_ssbo(&b, nir_imm_int(&b, 0), dst_buf, output_elem, .align_mul = 4);
nir_store_ssbo(&b, nir_imm_int(&b, 0), dst_buf, output_elem);
nir_pop_if(&b, NULL);
@@ -460,12 +459,11 @@ build_tfb_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .align_mul = 8);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base);
nir_push_else(&b, NULL);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base,
.align_mul = 4);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base);
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@@ -566,12 +564,11 @@ build_timestamp_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .align_mul = 8);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base);
nir_push_else(&b, NULL);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base,
.align_mul = 4);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base);
nir_pop_if(&b, NULL);
src/amd/vulkan/radv_shader.c
+1 -1
View File
@@ -329,7 +329,7 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key,
nir_channel(&b, intrin->src[0].ssa, 1)));
def = nir_build_load_global(&b, 1, 64, addr, .access = ACCESS_NON_WRITEABLE,
.align_mul = 8, .align_offset = 0);
.align_offset = 0);
} else {
def = nir_vector_insert_imm(&b, intrin->src[0].ssa, nir_imm_int(&b, 0), 2);
}