ail: Force page-alignment for layered attachments

When rendering to a layered depth/stencil attachment, we specify the layer
stride in pages. That means that depth/stencil targets must be page-aligned to
be rendered to correctly.

If we're merely sampling, not rendering, we do not need the extra alignment. So
we add a flag to handle this case so we keep passing the generated ail tests.

Fixes KHR-GLES31.core.texture_cube_map_array.color_depth_attachments

Similarly, we page-align colour attachments. I don't have a good theoretical
justification for this part, but it seems to be necessary and layered rendering
fails otherwise. Possibly the PBE requires page-aligned layers unconditionally?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

src/asahi/layout/layout.c

@@ -160,15 +160,17 @@ ail_initialize_twiddled(struct ail_layout *layout)
    layout->page_aligned_layers = layout->levels != 1 && offset_B > AIL_PAGESIZE;
 
    /* Single-layer images are not padded unless they are Z/S */
-   if (layout->depth_px == 1 &&
-       !util_format_is_depth_or_stencil(layout->format))
+   bool zs = util_format_is_depth_or_stencil(layout->format);
+   if (layout->depth_px == 1 && !zs)
       layout->page_aligned_layers = false;
 
    /* For writable images, we require page-aligned layers. This appears to be
-    * required for PBE stores.
+    * required for PBE stores, including block stores for colour rendering.
+    * Likewise, we specify the ZLS layer stride in pages, so we need
+    * page-aligned layers for renderable depth/stencil targets.
     */
-   if (layout->writeable_image)
-      layout->page_aligned_layers = true;
+   layout->page_aligned_layers |= layout->writeable_image;
+   layout->page_aligned_layers |= layout->renderable && layout->depth_px > 1;
 
    if (layout->page_aligned_layers)
       layout->layer_stride_B = ALIGN_POT(offset_B, AIL_PAGESIZE);

src/asahi/layout/layout.h

@@ -123,6 +123,11 @@ struct ail_layout {
     * used as a writeable image (either PBE or image atomics).
     */
    bool writeable_image;
+
+   /* Must the layout support rendering? If false, the layout MUST NOT be used
+    * for rendering, either PBE or ZLS.
+    */
+   bool renderable;
 };
 
 static inline uint32_t

src/gallium/drivers/asahi/agx_pipe.c

@@ -181,6 +181,13 @@ agx_resource_setup(struct agx_device *dev, struct agx_resource *nresource)
       .sample_count_sa = MAX2(templ->nr_samples, 1),
       .levels = templ->last_level + 1,
       .writeable_image = templ->bind & PIPE_BIND_SHADER_IMAGE,
+
+      /* Ostensibly this should be based on the bind, but Gallium bind flags are
+       * notoriously unreliable. The only cost of setting this excessively is a
+       * bit of extra memory use for layered textures, which isn't worth trying
+       * to optimize.
+       */
+      .renderable = true,
    };
 }