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i965: Explicitly set widths on gen5 math instruction destinations.

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Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
2014-09-25 12:06:42 -07:00
parent 004fbd5375
commit 5390ca8ce9
1 changed files with 1 additions and 1 deletions
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src/mesa/drivers/dri/i965/brw_fs.cpp
+1 -1
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@@ -1523,7 +1523,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
fs_reg &op0 = is_int_div ? src1 : src0;
fs_reg &op1 = is_int_div ? src0 : src1;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1);
emit(MOV(fs_reg(MRF, base_mrf + 1, op1.type, dispatch_width), op1));
inst = emit(opcode, dst, op0, reg_null_f);
inst->base_mrf = base_mrf;