radeonsi/sqtt: handle COMPUTE queues as well
Use cs_get_ip_type to support both type of queues instead of restricting ourselves to GFX. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26774>
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@@ -4,6 +4,7 @@
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* SPDX-License-Identifier: MIT
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*/
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#include "amd_family.h"
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#include "si_build_pm4.h"
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#include "si_pipe.h"
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@@ -49,7 +50,7 @@ static bool si_sqtt_init_bo(struct si_context *sctx)
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static void si_emit_sqtt_start(struct si_context *sctx,
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struct radeon_cmdbuf *cs,
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uint32_t queue_family_index)
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enum amd_ip_type ip_type)
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{
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struct si_screen *sscreen = sctx->screen;
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uint32_t shifted_size = sctx->sqtt->buffer_size >> SQTT_BUFFER_ALIGN_SHIFT;
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@@ -216,7 +217,7 @@ static void si_emit_sqtt_start(struct si_context *sctx,
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S_030800_INSTANCE_BROADCAST_WRITES(1));
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/* Start the thread trace with a different event based on the queue. */
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if (queue_family_index == AMD_IP_COMPUTE) {
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if (ip_type == AMD_IP_COMPUTE) {
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radeon_set_sh_reg(R_00B878_COMPUTE_THREAD_TRACE_ENABLE,
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S_00B878_THREAD_TRACE_ENABLE(1));
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} else {
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@@ -310,13 +311,13 @@ static void si_copy_sqtt_info_regs(struct si_context *sctx,
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}
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static void si_emit_sqtt_stop(struct si_context *sctx, struct radeon_cmdbuf *cs,
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uint32_t queue_family_index)
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enum amd_ip_type ip_type)
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{
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unsigned max_se = sctx->screen->info.max_se;
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radeon_begin(cs);
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/* Stop the thread trace with a different event based on the queue. */
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if (queue_family_index == AMD_IP_COMPUTE) {
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if (ip_type == AMD_IP_COMPUTE) {
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radeon_set_sh_reg(R_00B878_COMPUTE_THREAD_TRACE_ENABLE,
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S_00B878_THREAD_TRACE_ENABLE(0));
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} else {
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@@ -411,14 +412,14 @@ static void si_emit_sqtt_stop(struct si_context *sctx, struct radeon_cmdbuf *cs,
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radeon_end();
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}
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static void si_sqtt_start(struct si_context *sctx, int family,
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struct radeon_cmdbuf *cs)
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static void si_sqtt_start(struct si_context *sctx, struct radeon_cmdbuf *cs)
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{
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struct radeon_winsys *ws = sctx->ws;
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enum amd_ip_type ip_type = sctx->ws->cs_get_ip_type(cs);
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radeon_begin(cs);
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switch (family) {
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switch (ip_type) {
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case AMD_IP_GFX:
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radeon_emit(PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
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radeon_emit(CC0_UPDATE_LOAD_ENABLES(1));
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@@ -428,6 +429,9 @@ static void si_sqtt_start(struct si_context *sctx, int family,
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radeon_emit(PKT3(PKT3_NOP, 0, 0));
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radeon_emit(0);
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break;
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default:
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/* Unsupported. */
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assert(false);
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}
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radeon_end();
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@@ -457,20 +461,20 @@ static void si_sqtt_start(struct si_context *sctx, int family,
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si_emit_spm_setup(sctx, cs);
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}
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si_emit_sqtt_start(sctx, cs, family);
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si_emit_sqtt_start(sctx, cs, ip_type);
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if (sctx->spm.bo)
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si_pc_emit_spm_start(cs);
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}
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static void si_sqtt_stop(struct si_context *sctx, int family,
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struct radeon_cmdbuf *cs)
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static void si_sqtt_stop(struct si_context *sctx, struct radeon_cmdbuf *cs)
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{
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struct radeon_winsys *ws = sctx->ws;
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enum amd_ip_type ip_type = sctx->ws->cs_get_ip_type(cs);
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radeon_begin(cs);
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switch (family) {
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switch (ip_type) {
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case AMD_IP_GFX:
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radeon_emit(PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
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radeon_emit(CC0_UPDATE_LOAD_ENABLES(1));
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@@ -480,6 +484,9 @@ static void si_sqtt_stop(struct si_context *sctx, int family,
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radeon_emit(PKT3(PKT3_NOP, 0, 0));
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radeon_emit(0);
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break;
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default:
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/* Unsupported. */
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assert(false);
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}
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radeon_end();
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@@ -503,7 +510,7 @@ static void si_sqtt_stop(struct si_context *sctx, int family,
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SI_CONTEXT_PFP_SYNC_ME;
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sctx->emit_cache_flush(sctx, cs);
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si_emit_sqtt_stop(sctx, cs, family);
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si_emit_sqtt_stop(sctx, cs, ip_type);
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if (sctx->spm.bo)
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si_pc_emit_spm_reset(cs);
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@@ -518,40 +525,40 @@ static void si_sqtt_init_cs(struct si_context *sctx)
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{
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struct radeon_winsys *ws = sctx->ws;
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/* Thread trace start CS (only handles AMD_IP_GFX). */
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sctx->sqtt->start_cs[AMD_IP_GFX] = CALLOC_STRUCT(radeon_cmdbuf);
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if (!ws->cs_create(sctx->sqtt->start_cs[AMD_IP_GFX], sctx->ctx, AMD_IP_GFX,
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NULL, NULL)) {
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free(sctx->sqtt->start_cs[AMD_IP_GFX]);
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sctx->sqtt->start_cs[AMD_IP_GFX] = NULL;
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return;
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for (unsigned i = 0; i < ARRAY_SIZE(sctx->sqtt->start_cs); i++) {
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sctx->sqtt->start_cs[i] = CALLOC_STRUCT(radeon_cmdbuf);
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if (!ws->cs_create(sctx->sqtt->start_cs[i], sctx->ctx, (enum amd_ip_type)i,
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NULL, NULL)) {
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free(sctx->sqtt->start_cs[i]);
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sctx->sqtt->start_cs[i] = NULL;
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return;
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}
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si_sqtt_start(sctx, sctx->sqtt->start_cs[i]);
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sctx->sqtt->stop_cs[i] = CALLOC_STRUCT(radeon_cmdbuf);
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if (!ws->cs_create(sctx->sqtt->stop_cs[i], sctx->ctx, (enum amd_ip_type)i,
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NULL, NULL)) {
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ws->cs_destroy(sctx->sqtt->start_cs[i]);
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free(sctx->sqtt->start_cs[i]);
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sctx->sqtt->start_cs[i] = NULL;
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free(sctx->sqtt->stop_cs[i]);
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sctx->sqtt->stop_cs[i] = NULL;
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return;
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}
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si_sqtt_stop(sctx, sctx->sqtt->stop_cs[i]);
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}
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si_sqtt_start(sctx, AMD_IP_GFX, sctx->sqtt->start_cs[AMD_IP_GFX]);
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/* Thread trace stop CS. */
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sctx->sqtt->stop_cs[AMD_IP_GFX] = CALLOC_STRUCT(radeon_cmdbuf);
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if (!ws->cs_create(sctx->sqtt->stop_cs[AMD_IP_GFX], sctx->ctx, AMD_IP_GFX,
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NULL, NULL)) {
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free(sctx->sqtt->start_cs[AMD_IP_GFX]);
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sctx->sqtt->start_cs[AMD_IP_GFX] = NULL;
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free(sctx->sqtt->stop_cs[AMD_IP_GFX]);
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sctx->sqtt->stop_cs[AMD_IP_GFX] = NULL;
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return;
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}
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si_sqtt_stop(sctx, AMD_IP_GFX, sctx->sqtt->stop_cs[AMD_IP_GFX]);
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}
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static void si_begin_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs)
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{
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struct radeon_cmdbuf *cs = sctx->sqtt->start_cs[AMD_IP_GFX];
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struct radeon_cmdbuf *cs = sctx->sqtt->start_cs[sctx->ws->cs_get_ip_type(rcs)];
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sctx->ws->cs_flush(cs, 0, NULL);
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}
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static void si_end_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs)
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{
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struct radeon_cmdbuf *cs = sctx->sqtt->stop_cs[AMD_IP_GFX];
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struct radeon_cmdbuf *cs = sctx->sqtt->stop_cs[sctx->ws->cs_get_ip_type(rcs)];
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sctx->ws->cs_flush(cs, 0, &sctx->last_sqtt_fence);
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}
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@@ -668,8 +675,10 @@ void si_destroy_sqtt(struct si_context *sctx)
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if (sctx->sqtt->trigger_file)
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free(sctx->sqtt->trigger_file);
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sscreen->ws->cs_destroy(sctx->sqtt->start_cs[AMD_IP_GFX]);
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sscreen->ws->cs_destroy(sctx->sqtt->stop_cs[AMD_IP_GFX]);
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for (int i = 0; i < ARRAY_SIZE(sctx->sqtt->start_cs); i++) {
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sscreen->ws->cs_destroy(sctx->sqtt->start_cs[i]);
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sscreen->ws->cs_destroy(sctx->sqtt->stop_cs[i]);
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}
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struct rgp_pso_correlation *pso_correlation =
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&sctx->sqtt->rgp_pso_correlation;
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