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intel/isl: Add ASTC HDR to format lists and helpers

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Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Nanley Chery
2017-05-16 16:20:59 -07:00
parent b2c5e69942
commit 52a6fd9871
3 changed files with 58 additions and 2 deletions
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src/intel/isl/isl.h
+14
View File
@@ -353,6 +353,20 @@ enum isl_format {
ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
/* The formats that follow are internal to ISL and as such don't have an
* explicit number. We'll just let the C compiler assign it for us. Any
src/intel/isl/isl_format.c
+30 -2
View File
@@ -341,6 +341,20 @@ static const struct surface_format_info format_info[] = {
SF(90, 90, x, x, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X10_U8SRGB)
SF(90, 90, x, x, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X10_U8SRGB)
SF(90, 90, x, x, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X12_U8SRGB)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_4X4_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_5X4_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_5X5_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_6X5_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_6X6_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_8X5_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_8X6_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_8X8_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X5_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X6_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X8_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X10_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_12X10_FLT16)
SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_12X12_FLT16)
};
#undef x
#undef Y
@@ -387,9 +401,16 @@ isl_format_supports_sampling(const struct gen_device_info *devinfo,
return true;
} else if (devinfo->is_cherryview) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC exists on Cherry View even though big-core
/* Support for ASTC LDR exists on Cherry View even though big-core
* GPUs didn't get it until Skylake.
*/
if (fmtl->txc == ISL_TXC_ASTC)
return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
} else if (devinfo->is_broxton) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC HDR exists on Broxton even though big-core
* GPUs didn't get it until Cannonlake.
*/
if (fmtl->txc == ISL_TXC_ASTC)
return true;
}
@@ -413,9 +434,16 @@ isl_format_supports_filtering(const struct gen_device_info *devinfo,
return true;
} else if (devinfo->is_cherryview) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC exists on Cherry View even though big-core
/* Support for ASTC LDR exists on Cherry View even though big-core
* GPUs didn't get it until Skylake.
*/
if (fmtl->txc == ISL_TXC_ASTC)
return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
} else if (devinfo->is_broxton) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC HDR exists on Broxton even though big-core
* GPUs didn't get it until Cannonlake.
*/
if (fmtl->txc == ISL_TXC_ASTC)
return true;
}
src/intel/isl/isl_format_layout.csv
+14
View File
@@ -314,6 +314,20 @@ ASTC_LDR_2D_10X8_FLT16 , 128, 10, 8, 1, sf16, sf16, sf16, sf16, ,
ASTC_LDR_2D_10X10_FLT16 , 128, 10, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_LDR_2D_12X10_FLT16 , 128, 12, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_LDR_2D_12X12_FLT16 , 128, 12, 12, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_4X4_FLT16 , 128, 4, 4, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_5X4_FLT16 , 128, 5, 4, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_5X5_FLT16 , 128, 5, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_6X5_FLT16 , 128, 6, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_6X6_FLT16 , 128, 6, 6, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_8X5_FLT16 , 128, 8, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_8X6_FLT16 , 128, 8, 6, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_8X8_FLT16 , 128, 8, 8, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_10X5_FLT16 , 128, 10, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_10X6_FLT16 , 128, 10, 6, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_10X8_FLT16 , 128, 10, 8, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_10X10_FLT16 , 128, 10, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_12X10_FLT16 , 128, 12, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc
ASTC_HDR_2D_12X12_FLT16 , 128, 12, 12, 1, sf16, sf16, sf16, sf16, , , , linear, astc
HIZ , 128, 8, 4, 1, , , , , , , , , hiz
MCS_2X , 8, 1, 1, 1, , , , , , , , , mcs
MCS_4X , 8, 1, 1, 1, , , , , , , , , mcs
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