radv: Pass correct queue family to radv_cs_emit_write_event_eop
Probably a leftover from a previous code refactor. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37775>
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@@ -410,7 +410,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e
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/* Necessary for DCC */
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if (gfx_level >= GFX8) {
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radv_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM,
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radv_cs_emit_write_event_eop(cs, gfx_level, qf, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM,
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EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va);
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}
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@@ -497,7 +497,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e
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assert(flush_cnt);
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(*flush_cnt)++;
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radv_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
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radv_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
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EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va);
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radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff);
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}
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