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freedreno/registers: Add RBBM_GPR0_CNTL for non-GMU operation

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Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20925>
This commit is contained in:
Konrad Dybcio
2023-01-25 22:42:42 +01:00
committed by Marge Bot
parent f9bcf19e52
commit 50dee85b68
2 changed files with 2 additions and 1 deletions
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src/freedreno/.gitlab-ci/reference/crash.log
+1 -1
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@@ -138,7 +138,7 @@ registers:
02402892 0x2: 02402892
00000003 RBBM_VBIF_CLIENT_QOS_CNTL: 0x3
00000000 0x12: 00000000
00000000 0x18: 00000000
00000000 RBBM_GPR0_CNTL: 0
00000000 0x19: 00000000
00000030 0x1a: 00000030
00000030 0x1b: 00000030
src/freedreno/registers/adreno/a6xx.xml
+1
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@@ -1115,6 +1115,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
<reg32 offset="0x0210" name="RBBM_STATUS">
<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>